TC55VCM208ASTN40,55
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VCM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by
8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7
µA
standby
current (at V
DD
=
3 V, Ta
=
25°C, typical) when chip enable (
CE1
) is asserted high or (CE2) is asserted low. There
are three control inputs.
CE1
and CE2 are used to select the device and for data retention control, and output
enable (
OE
) provides fast memory access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
−40°
to 85°C, the TC55VCM208ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VCM208ASTN is available in a plastic 40-pin thin-small outline package
(TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using
CE1
and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum):
3.6 V
3.0 V
10
µA
5
µA
•
Access Times:
TC55VCM208ASTN
40
Access Time
CE1 Access Time
CE2
OE
Access Time
Access Time
40 ns
40 ns
40 ns
25 ns
55
55 ns
55 ns
55 ns
30 ns
•
Package:
TSOPⅠ40-P-1014-0.50
(Weight:0.30 g typ)
PIN ASSIGNMENT
(TOP VIEW)
40 PIN TSOP
PIN NAMES
A0~A18
Address Inputs
1
40
CE1 , CE2
R/W
OE
LB , UB
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Option
20
(Normal)
21
I/O1~I/O16
V
DD
GND
NC
OP*
*
: OP pin must be open or connected to GND.
Pin No.
Pin Name
Pin No.
Pin Name
1
A16
21
A0
2
A15
22
CE1
3
A14
23
GND
4
A13
24
OE
5
A12
25
I/O1
6
A11
26
I/O2
7
A9
27
I/O3
8
A8
28
I/O4
9
R/W
29
NC
10
CE2
30
V
DD
11
OP
31
V
DD
12
NC
32
I/O5
13
A18
33
I/O6
14
A7
34
I/O7
15
A6
35
I/O8
16
A5
36
A10
17
A4
37
NC
18
A3
38
NC
19
A2
39
GND
20
A1
40
A17
2003-08-11
1/12
TC55VCM208ASTN40,55
BLOCK DIAGRAM
CE
A6
A7
A8
A9
A11
A12
A13
A14
A15
A16
A18
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
V
DD
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
GND
MEMORY CELL ARRAY
2,048
×
256
×
8
(4,194,304)
SENSE AMP
DATA
CONTROL
COLUMN ADDRESS
DECODER
CLOCK
GENERATOR
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A4 A5 A10 A17
OE
R/W
CE1
CE2
CE
OPERATING MODE
MODE
Read
Write
Output Deselect
Standby
*
= don't care
H = logic high
L = logic low
CE1
L
L
L
H
*
CE2
H
H
H
*
OE
L
*
R/W
H
L
H
*
*
I/O1~I/O8
Output
Input
High-Z
High-Z
High-Z
POWER
I
DDO
I
DDO
I
DDO
I
DDS
I
DDS
H
*
*
L
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
−
0.3~4.2
−
0.3
*
~4.2
−
0.5~V
DD
+
0.5
UNIT
V
V
V
W
°C
°C
°C
0.6
260
−
55~150
−
40~85
*
:
−
2.0 V when measured at a pulse width of 20ns
2003-08-11
2/12
TC55VCM208ASTN40,55
DC RECOMMENDED OPERATING CONDITIONS (
Ta
= −40°
to 85°C
)
SYMBOL
V
DD
V
IH
V
IL
V
DH
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
V
DD
=
2.3 V~2.7 V
V
DD
=
2.7 V~3.6 V
MIN
2.3
2.0
2.2
−
0.3
*
TYP
MAX
3.6
V
DD
+
0.3
V
DD
×
0.24
3.6
UNIT
V
V
V
V
1.5
*
:
−
2.0 V when measured at a pulse width of 20ns
DC CHARACTERISTICS
(Ta
= −40°
to 85°C, V
DD
=
2.3 to 3.6 V)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
V
IN
=
0 V~V
DD
TEST CONDITION
MIN
−
0.5
TYP
MAX UNIT
±
1.0
±
1.0
µ
A
Output High Current V
OH
=
V
DD
−
0.5 V
Output Low Current
Output Leakage
Current
V
OL
=
0.4 V
CE1
=
V
IH
or CE2
=
V
IL
or R/W
=
V
IL
or OE
=
V
IH
,
V
OUT
=
0 V~V
DD
CE1
=
V
IL
and CE2
=
V
IH
and
R/W
=
V
IH
, I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
Operating Current
CE1
=
0.2 V and
CE2
=
V
DD
−
0.2 V and
R/W
=
V
DD
−
0.2 V,
I
OUT
=
0 mA,
Other Input
=
V
DD
−
0.2 V/0.2 V
CE1
=
V
IH
or CE2
=
V
IL
V
DD
=
Ta
= −
40~85°C
3.3V
±
0.3 V
Standby Current
t
cycle
MIN
1
µ
s
MIN
mA
mA
µ
A
2.1
35
mA
8
30
mA
I
DDO1
I
DDO2
1
µ
s
3
1
10
µ
A
I
DDS1
mA
I
DDS2
CE1
=
V
DD
−
0.2 V or
CE2
=
0.2 V
Ta
=
25°C
V
DD
=
3.0 V Ta
= −
40~40°C
Ta
= −
40~85°C
0.7
2
5
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
2003-08-11
3/12
TC55VCM208ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= −40°
to 85°C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
40
40
MAX
55
MIN
55
UNIT
MAX
40
40
40
25
55
55
55
30
ns
5
0
5
0
20
20
25
25
10
10
WRITE CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Note:
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
40
30
35
0
0
40
MAX
55
MIN
55
40
45
0
0
UNIT
MAX
ns
20
25
0
20
0
0
25
0
t
OD
, t
ODO
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
2003-08-11
4/12
TC55VCM208ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= −40°
to 85°C, V
DD
=
2.3 to 3.6 V)
READ CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
55
40
MAX
55
MIN
70
UNIT
MAX
55
55
55
30
70
70
70
35
ns
5
0
5
0
25
25
30
30
10
10
WRITE CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Note:
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
55
40
45
0
0
40
MAX
55
MIN
70
50
55
0
0
UNIT
MAX
ns
25
30
0
25
0
0
30
0
t
OD
, t
ODO
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
2003-08-11
5/12
MicroPython开源版块
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
