TC55V040AFT-55,-70
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V040AFT is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5
µA
standby
current (at V
DD
=
3 V, Ta
=
25°C, maximum) when chip enable (
CE1
) is asserted high or (CE2) is asserted low.
There are three control inputs.
CE1
and CE2 are used to select the device and for data retention control, and
output enable (
OE
) provides fast memory access. This device is well suited to various microprocessor system
applications where high speed, low power and battery backup are required. And, with a guaranteed operating
extreme temperature range of
−40°
to 85°C, the TC55V040AFT can be used in environments exhibiting extreme
temperature conditions. The TC55V040AFT is available in normal and reverse pinout plastic 40-pin
thin-small-outline package (TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 10.8 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using
CE1
and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum):
3.6 V
3.0 V
7
µA
5
µA
•
Access Times (maximum):
TC55V040AFT
-55
Access Time
CE1 Access Time
CE2 Access Time
OE Access Time
55 ns
55 ns
55 ns
30 ns
-70
70 ns
70 ns
70 ns
35 ns
•
Package:
TSOPⅠ40-P-1014-0.50 (AFT) (Weight: 0.32 g typ)
PIN ASSIGNMENT
(TOP VIEW)
40 PIN TSOP
1
40
PIN NAMES
A0~A18
Address Inputs
CE1 , CE2
R/W
OE
20
(Normal)
21
I/O1~I/O8
V
DD
GND
NC
Chip Enable
Read/Write Control
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
Pin No.
Pin Name
Pin No.
Pin Name
1
A16
21
A0
2
A15
22
CE1
3
A14
23
GND
4
A13
24
OE
5
A12
25
I/O1
6
A11
26
I/O2
7
A9
27
I/O3
8
A8
28
I/O4
9
R/W
29
NC
10
CE2
30
V
DD
11
NC
31
V
DD
12
NC
32
I/O5
13
A18
33
I/O6
14
A7
34
I/O7
15
A6
35
I/O8
16
A5
36
A10
17
A4
37
NC
18
A3
38
NC
19
A2
39
GND
20
A1
40
A17
2003-08-06
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TC55V040AFT-55,-70
DC RECOMMENDED OPERATING CONDITIONS
(Ta
= −40°
to 85°C)
2.3 V~3.6 V
SYMBOL
PARAMETER
MIN
V
DD
V
IH
V
IL
V
DH
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
2.3
2.2
−
0.3
*
UNIT
TYP
3.0
MAX
3.6
V
DD
+
0.3
V
DD
×
0.22
3.6
V
V
V
V
1.5
*
:
−
3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS
(Ta
= −40°
to 85°C, V
DD
=
2.3 to 3.6 V)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage
Current
V
IN
=
0 V~V
DD
V
OH
=
V
DD
−
0.5 V
V
OL
=
0.4 V
CE1
=
V
IH
or CE2
=
V
IL
or R/W
=
V
IL
or OE
=
V
IH
,
V
OUT
=
0 V~V
DD
CE1
=
V
IL
and CE2
=
V
IH
and
R/W
=
V
IH
and I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
Operating Current
l
DDO2
CE1
=
0.2 V and
CE2
=
V
DD
−
0.2 V and
V
DD
=
t
cycle
R/W
=
V
DD
−
0.2 V, I
OUT
=
0 mA, 3 V
±
10%
Other Input
=
V
DD
−
0.2 V/0.2 V
CE
=
V
IH
or CE2
=
V
IL
V
DD
=
3 V
±
10%
Standby Current
CE1
=
V
DD
−
0.2 V
or CE2
=
0.2 V
V
DD
=
1.5 V~3.6 V
V
DD
=
3.3 V
±
0.3 V
Ta
=
25°C
Ta
= −
40~85°C
Ta
=
25°C
Ta
= −
40~85°C
Ta
=
25°C
V
DD
=
3.0 V
Ta
= −
40~40°C
Ta
= −
40~85°C
Note:
55 ns
70 ns
1
µ
s
55 ns
V
DD
=
t
cycle
3 V
±
10%
70 ns
1
µ
s
TEST CONDITION
MIN
−
0.5
TYP
MAX
±
1.0
±
1.0
UNIT
µ
A
mA
mA
µ
A
2.1
60
50
10
55
45
5
2
0.6
6
0.7
7
0.5
1
5
µ
A
l
DDO1
mA
mA
I
DDS1
mA
I
DDS2
(Note)
0.05
In standby mode with CE1
≥
V
DD
−
0.2 V, these limits are assured for the condition CE2
≥
V
DD
−
0.2 V or CE2
≤
0.2 V.
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
2003-08-06
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TC55V040AFT-55,-70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= −40°
to 85°C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55V040AFT
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
55
-55
MAX
-70
MIN
70
UNIT
MAX
55
55
55
30
70
70
70
35
ns
5
0
5
0
25
25
30
30
10
10
WRITE CYCLE
TC55V040AFT
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
55
45
50
0
0
-55
MAX
-70
MIN
70
50
60
0
0
UNIT
MAX
ns
25
30
0
25
0
0
30
0
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
30 pF
+
1 TTL Gate
0.4 V, 2.4 V
V
DD
×
0.5
V
DD
×
0.5
5 ns
2003-08-06
4/11
TC55V040AFT-55,-70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= −40°
to 85°C, V
DD
=
2.3 to 3.6 V)
READ CYCLE
TC55V040AFT
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
70
-55
MAX
-70
MIN
85
UNIT
MAX
70
70
70
35
85
85
85
45
ns
5
0
5
0
30
30
35
35
10
10
WRITE CYCLE
TC55V040AFT
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
70
50
60
0
0
-55
MAX
-70
MIN
85
55
70
0
0
UNIT
MAX
ns
30
35
0
30
0
0
35
0
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
30 pF
+
1 TTL Gate
V
DD
−
0.2 V, 0.2 V
V
DD
×
0.5
V
DD
×
0.5
5 ns
2003-08-06
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