256MB, 512MB, 1GB (x64, DR)
PC2-3200, PC2-4200, 200-Pin DDR2 SDRAM SODIMM
DDR2 SDRAM
SODIMM
Features
• 200-pin, small outline, dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2-3200 or PC2-4200
• Utilizes 400 MT/s and 533 MT/s DDR2 SDRAM
components
• 256MB (32 Meg x 64), 512MB (64 Meg x 64)
1GB (128 Meg x 64)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL): 3 and 4
• Posted CAS# additive latency (AL): 0, 1, 2, 3, and 4
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial Presence Detect (SPD) with EEPROM
• Gold edge contacts
MT8HTF3264HD – 256MB
MT8HTF6464HD – 512MB (PRELIMINARY
‡
)
MT8HTF12864HD – 1GB (PRELIMINARY
‡
)
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 200-Pin SODIMM (MO-224 R/C “A”)
1.18in. (29.97mm)
OPTIONS
MARKING
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
1
• Frequency/CAS Latency
2
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB
1.18in. (29.97mm)
NOTE:
G
Y
-53E
-40E
1. Consult factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) Latency.
Table 1:
Address Table
256MB
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
1KB
512Mb (32 Meg x 16)
1K (A0-A9)
2 (S0#, S1#)
1GB
8K
8K (A0–A12)
8 (BA0, BA1, BA2)
1KB
1Gb (64 Meg x 16)
1K (A0-A9)
2 (S0#, S1#)
8K
8K (A0–A12)
4 (BA0, BA1)
1KB
256Mb (16 Meg x 16)
512 (A0-A8)
2 (S0#, S1#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Page Size per Bank
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80ebed66, source: 09005aef80ebbc49
HTF8C32_64_128x64HDG.fm - Rev. A 8/04 EN
1
©2004 Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
256MB, 512MB, 1GB (x64, DR)
PC2-3200, PC2-4200, 200-Pin DDR2 SDRAM SODIMM
Table 2:
Key Timing Parameters
DATA RATE (MHz)
SPEED GRADE
-53E
-40E
CL = 3
400
400
CL = 4
533
400
t
RCD
(ns)
15
15
RP
(ns)
15
15
t
RC
(ns)
60
55
t
Table 3:
Part Numbers and Timing Parameters
MODULE
DENSITY
256MB
256MB
256MB
256MB
512MB
512MB
1GB
1GB
CONFIGURATION
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
64 Meg x 64
64 Meg x 64
128 Meg x 64
128 Meg x 64
MODULE
BANDWIDTH
3.2 GB/s
3.2 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
4.3 GB/s
3.2 GB/s
4.3 GB/s
MEMORY CLOCK/
DATA RATE
5.0ns/400 MT/s
5.0ns/400 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
3.75ns/533 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
3-3-3
3-3-3
4-4-4
4-4-4
3-3-3
4-4-4
3-3-3
4-4-4
PART NUMBER
1
MT8HTF3264HDG-40E__
MT8HTF3264HDY-40E__
MT8HTF3264HDG-53E__
MT8HTF3264HDY-53E__
MT8HTF6464HDY-40E__
2
MT8HTF6464HDY-53E__
2
MT8HTF12864HDY-40E__
2
MT8HTF12864HDY-53E__
2
NOTE:
1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory
for current revision codes. Example: MT8HTF6464HDG-40EC2.
2. Contact Micron for product availability.
pdf: 09005aef80ebed66, source: 09005aef80ebbc49
HTF8C32_64_128x64HDG.fm - Rev. A 8/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
256MB, 512MB, 1GB (x64, DR)
PC2-3200, PC2-4200, 200-Pin DDR2 SDRAM SODIMM
Table 4:
Pin Assignment
(200-pin SODIMM Front)
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
NC/BA2
V
DD
A12
A9
A8
V
DD
A5
A3
101
A1
151
103
V
DD
153
105 A10/AP
155
107
BA0
157
109
WE#
159
111
V
DD
161
113 CAS#
163
115
S1#
165
117
V
DD
167
119 ODT1 169
121
V
SS
171
123
DQ32
173
125
DQ33 175
127
V
SS
177
129 DQS4#
179
131 DQS4
181
133
V
SS
183
135 DQ34
185
137 DQ35
187
139
V
SS
189
141 DQ40
191
143 DQ41 193
145
V
SS
195
147 DM5 197
149
V
SS
199
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
Table 5:
Pin Assignment
(200-pin SODIMM Back)
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A0
V
DD
BA1
RAS#
S0#
V
DD
ODT0
NC
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
CK1#
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0#
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
Vss
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2#
Pin 85 is NC for 256MB and 512MB, BA2 for 1GB.
Figure 2: Pin Locations
Front View
Back View
U1
U2
U3
U4
U5
U6
U8
U9
U7
PIN 1
(all odd pins)
PIN 199
PIN 200
(all even pins)
PIN 2
Indicates a VDD or VDDQ pin
Indicates a VSS pin
pdf: 09005aef80ebed66, source: 09005aef80ebbc49
HTF8C32_64_128x64HDG.fm - Rev. A 8/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
256MB, 512MB, 1GB (x64, DR)
PC2-3200, PC2-4200, 200-Pin DDR2 SDRAM SODIMM
Table 6:
PIN NUMBERS
114, 119
Pin Descriptions
SYMBOL
ODT0, ODT1
TYPE
Input
DESCRIPTION
On-Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock Enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry, POWER-DOWN exit, output disable, and
for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH
exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_18 input but
will detect a LVCMOS LOW level once V
DD
is applied during first
power-up. After Vref has become stable during the power on
and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh operation
V
REF
must be maintained to this input.
Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when
S# is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the
command code.
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank Address Inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied BA0–BA1/BA2 define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for Read/
Write commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
30, 32, 164, 166
CK0, CK0#
CK1, CK1#
Input
79, 80
CKE0, CKE1
Input
110, 115
S0#, S1#
Input
108, 109, 113
85
(1GB),
106, 107
RAS#, CAS#, WE#
BA0, BA1,
BA2
(1GB)
Input
Input
89, 90, 91, 92, 93, 94, 97, 98,
99, 100, 101, 102, 105
A0–A12
Input
10, 26, 52, 67, 130, 147, 170,
DM0–DM7
185
UDM = DM0, DM2,
DM5, DM7
LDM = DM 1, DM3,
DM4, DM6
Input
pdf: 09005aef80ebed66, source: 09005aef80ebbc49
HTF8C32_64_128x64HDG.fm - Rev. A 8/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
256MB, 512MB, 1GB (x64, DR)
PC2-3200, PC2-4200, 200-Pin DDR2 SDRAM SODIMM
Table 6:
PIN NUMBERS
4, 5, 6, 7, 14, 16, 17, 19, 20,
22, 23, 25, 35, 36, 37, 38, 43,
44, 45, 46, 55, 56, 57, 58, 61,
62, 63, 64, 73, 74, 75, 76,
123, 124, 125, 126, 134, 135,
136, 137, 140, 141, 142, 143,
151, 152, 153, 154, 157, 158,
159, 160, 173, 174, 175, 176,
179, 180, 181, 182, 189, 191,
192, 194
11, 13, 29, 31, 49, 51, 68, 70,
129, 131, 146, 148, 167, 169,
186, 188
Pin Descriptions
SYMBOL
DQ0–DQ63
TYPE
I/O
DESCRIPTION
Data Input/Output: Bidirectional data bus.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
DQS0–DQS7,
DQS0#–DQS7#
197
198, 200
195
SCL
SA0–SA1
SDA
81, 82, 87, 88, 95, 96, 103,
104, 111, 112, 117, 118
1
2, 3, 8, 9, 12, 15, 18, 21, 24,
27, 28, 33, 34, 39, 40, 41, 42,
47, 48, 53, 54, 59, 60, 65, 66,
71, 72, 77, 78, 121, 122, 127,
128, 132, 133, 138, 139, 144,
145, 149, 150, 155, 156, 161,
162, 165, 168, 171, 172, 177,
178, 183, 184, 187, 190, 193,
196
199
50, 69, 83, 84, 85 (256MB
and 512MB), 86, 116, 120,
163,
V
DD
V
REF
V
SS
Data Strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Input Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-detect
portion of the module.
Supply Power Supply: +1.8V ±0.1V.
Supply SSTL_18 reference voltage.
Supply Ground.
I/O
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
—
No Connect: These pins should be left unconnected.
pdf: 09005aef80ebed66, source: 09005aef80ebbc49
HTF8C32_64_128x64HDG.fm - Rev. A 8/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
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