MAIN FEATURES
8-bit resolution.
ADC gain adjust.
1.5 GHz full power input bandwidth.
1 Gsps (min) sampling rate.
SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc
@ F
S
= 1 Gsps, F
IN
= 20 MHz :
SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc
@ F
S
= 1 Gsps, F
IN
= 500 MHz :
SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc
@ F
S
= 1 Gsps, F
IN
= 1000 MHz (-3 dB FS)
2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.
DNL = 0.3 LSB
INL = 0.7 LSB.
-13
Low Bit Error Rate (10 ) @ 1 Gsps
Very low input capacitance : 3 pF
500 mVpp differential or single-ended analog inputs.
Differential or single-ended 50Ω ECL compatible clock inputs.
ECL or LVDS/HSTL output compatibility.
Data ready output with asynchronous reset.
Gray or Binary selectable output data ; NRZ output mode.
Power consumption :
3.4 W @ Tj = 70°C typical
CQFP package enhanced with heatspreader : Rthjc = 1.56°C/W
Dual power supply : ± 5 V
Radiation tolerance oriented design (150 Krad (Si) measured).
ADC 8-bit 1 Gsps
TS8388BFS
1/ Die form : JTS8388B
2/ Evaluation board :
TSEV8388BF
3/ Demultiplexer :
TS81102G0 : companion device available
APPLICATIONS
Digital Sampling Oscilloscopes.
Satellite receiver.
Electronic countermeasures / Electronic warfare.
Direct RF down–conversion.
SCREENING
Mil-PRF-38535, QML level Q for package version, DSCC 5962-0050401QYC
Space screening according to ESA/SCC 9000.
Temperature range: up to -55°C < Tc ; Tj < +125°C
DESCRIPTION
The TS8388BFS is a monolithic 8–bit analog–to–digital converter, designed for
digitizing wide bandwidth analog signals at very high sampling rates of up to 1
Gsps.
The TS8388BFS is using an innovative architecture, including an on chip Sample
and Hold (S/H), and is fabricated with an advanced high speed bipolar process.
The on–chip S/H has a 1.5 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
January 2002
FS Suffix : CQFP 68
Ceramic Quad Flat Pack
With heatspreader
Product Specification
Product Specification
TABLE OF CONTENTS
1.
2.
3.
SIMPLIFIED BLOCK DIAGRAM ....................................................................................................................................3
FUNCTIONAL DESCRIPTION ........................................................................................................................................3
SPECIFICATIONS ..............................................................................................................................................................4
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW).................................................................................................................... 4
RECOMMENDED CONDITIONS OF USE ............................................................................................................................................. 4
ELECTRICAL OPERATING CHARACTERISTICS................................................................................................................................. 5
TIMING DIAGRAMS................................................................................................................................................................................ 9
EXPLANATION OF TEST LEVELS ...................................................................................................................................................... 10
FUNCTIONS DESCRIPTION................................................................................................................................................................ 10
DIGITAL OUTPUT CODING ................................................................................................................................................................. 10
TS8388BFS PIN DESCRIPTION .......................................................................................................................................................... 11
TS8388BFS PINOUT ............................................................................................................................................................................ 12
OUTLINE DIMENSIONS – 68 PINS CQFP .......................................................................................................................................... 13
THERMAL CHARACTERISTICS .......................................................................................................................................................... 14
STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MH
Z
......................................................................................................................... 15
EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION ..................................................................................... 16
TYPICAL FFT RESULTS ...................................................................................................................................................................... 17
SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE ................................................................................................ 18
DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY ............................................................................................. 20
EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY .................................................................................. 21
SFDR VERSUS SAMPLING FREQUENCY ......................................................................................................................................... 21
TS8388BFS ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE ................................................................................... 22
TYPICAL FULL POWER INPUT BANDWIDTH .................................................................................................................................... 23
ADC STEP RESPONSE................................................................................................................................................................... 24
4.
PACKAGE DESCRIPTION. ............................................................................................................................................11
4.1.
4.2.
4.3.
4.4.
5.
TYPICAL CHARACTERIZATION RESULTS .............................................................................................................15
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
6.
7.
DEFINITION OF TERMS ................................................................................................................................................25
TS8388BFS MAIN FEATURES .......................................................................................................................................27
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
TIMING INFORMATIONS ..................................................................................................................................................................... 27
PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND............................................................................ 28
ANALOG INPUTS (VIN) (VINB) ............................................................................................................................................................ 28
CLOCK INPUTS (CLK) (CLKB) ............................................................................................................................................................ 29
NOISE IMMUNITY INFORMATIONS.................................................................................................................................................... 32
DIGITAL OUTPUTS .............................................................................................................................................................................. 32
OUT OF RANGE BIT
................................................................................................................................................................................... 34
GRAY OR BINARY OUTPUT DATA FORMAT SELECT...................................................................................................................... 35
DIODE PIN 49 ....................................................................................................................................................................................... 35
ADC GAIN CONTROL PIN 60.......................................................................................................................................................... 36
8.
EQUIVALENT INPUT / OUTPUT SCHEMATICS ......................................................................................................37
8.1.
EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS ................................................................................................ 37
8.2.
EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS................................................................................... 37
8.3.
EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS .................................................................................. 38
ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS.......................................................................................... 38
8.5.
GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS.............................................................................................. 39
8.6.
DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS .............................................................................................. 39
9.
10.
TSEV8388BFS : DEVICE EVALUATION BOARD ......................................................................................................40
ORDERING INFORMATION .....................................................................................................................................41
PACKAGE DEVICE .......................................................................................................................................................................... 41
EVALUATION BOARD ..................................................................................................................................................................... 41
10.1.
10.2.
2
TS8388BFS
TS8388BFS
1.
SIMPLIFIED BLOCK DIAGRAM
GAIN
MASTER/SLAVE TRACK & HOLD
VIN,VINB
G=2
T/H
G=1
T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
4
INTERPOLATION
STAGES
4
5
REGENERATION
LATCHES
4
ERROR CORRECTION &
DECODE LOGIC
8
OUTPUT LATCHES &
BUFFERS
8
DRRB DR,DRB
GORB
DATA,DATAB OR,ORB
5
CLK, CLKB
CLOCK
BUFFER
2.
FUNCTIONAL DESCRIPTION
The TS8388BFS is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 GHz.
The TS8388BFS includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation
circuitry.
Successive banks of
latches are regenerating the analog residues into logical data before entering an error correction circuitry and a
resynchronization stage followed by 75
Ω
differential output buffers.
The TS8388BFS works in fully differential mode from analog inputs up to digital outputs.
The TS8388BFS features a full power input bandwidth of 1.5 GHz.
Control pin GORB is provided to select either Gray or Binary data output format.
Gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388BFS.
The TS8388BFS uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation
tolerance (no performance drift measured at 150kRad total dose).
Product Specification
3
Product Specification
3.
SPECIFICATIONS
3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW)
Parameter
Positive supply voltage
Digital negative supply
voltage
Digital positive supply
voltage
Negative supply voltage
Maximum difference
between negative supply
voltages
Analog input voltages
Maximum difference
between V
IN
and V
INB
Digital input voltage
Digital input voltage
Digital output voltage
Clock input voltage
Maximum difference
between V
CLK
and V
CLKB
Maximum junction
temperature
Storage temperature
Lead temperature
(soldering 10s)
Notes :
Symbol
V
CC
DV
EE
V
PLUSD
V
EE
DV
EE
to V
EE
Comments
Value
GND to 6
GND to -5.7
GND-0.3 to 2.8
GND to -6
0.3
Unit
V
V
V
V
V
V
IN
or V
INB
V
IN -
V
INB
V
D
V
D
Vo
V
CLK
or V
CLKB
V
CLK -
V
CLKB
T
j
T
stg
T
leads
GORB
DRRB
-1 to +1
-2 to +2
-0.3 to V
CC
+0.3
V
EE
-0.3 to +0.9
V
PLUSD
-3 to V
PLUSD
-0.5
-3 to +1.5
-2 to +2
+135
-65 to +150
+300
V
V
V
V
V
V
V
o
C
C
C
o
o
Absolute maximum ratings are limiting values (referenced to GND=0V), to be applied individually, while other parameters are within
specified operating conditions. Long exposure to maximum rating may affect device reliability.
The use of a thermal heat sink is mandatory (see Thermal characteristics).
3.2. RECOMMENDED CONDITIONS OF USE
Parameter
Positive supply voltage
Positive digital supply voltage
Symbol
V
CC
V
PLUSD
V
PLUSD
Negative supply voltages
Differential analog input voltage
(Full Scale)
Clock input power level
Operating temperature range
V
EE, DVEE
V
IN,
V
INB
V
IN
-V
INB
P
CLK
P
CLKB
T
J
50
Ω
single–ended clock input
Commercial grade: “C”
Industrial grade: “V”
Military grade: “M”
50
Ω
differential or single-ended
ECL output compatibility
LVDS output compatibility
+1.4
-5.25
±113
450
3
Comments
Min.
4.75
Typ.
+5
GND
+2.4
-5.0
±125
500
4
0° < Tc ; Tj < 90°
-40° < Tc ; Tj < 110°
-55° < Tc ; Tj < +125
+2.6
-4.75
±137
550
10
Max.
5.25
Unit
V
V
V
V
mV
mVpp
dBm
o
C
4
TS8388BFS
TS8388BFS
3.3. ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = -5 V ; V
CC
= +5 V ; V
IN
-V
INB
= 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50
Ω
differentially terminated ;
Tj (typical) = 70°C. Full Temperature Range: up to –55°C<Tc; Tj<+125°C.
Parameter
POWER REQUIREMENTS
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
Positive supply current
Analog
Digital
Negative supply voltage
Negative supply current
Analog
Digital
Nominal power dissipation
Power supply rejection ratio
RESOLUTION
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage )
Full Scale Input Voltage range (single–ended input option )
(see Application
Notes)
Analog input capacitance
Input bias current
Input Resistance
Full Power input Bandwidth
Small Signal input Bandwidth (10 % full scale)
CLOCK INPUTS
Logic compatibility for clock inputs
(see Application Notes)
ECL Clock inputs voltages (V
CLK
or V
CLKB
) :
•
•
•
•
Logic “0” voltage
Logic “1” voltage
Logic “0” current
Logic “1” current
(note 10 )
(note 2)
Symb
Test
level
Min
Typ
Max
Unit
VCC
V
PLUSD
V
PLUSD
ICC
I
PLUSD
VEE
AIEE
DIEE
PD
PSRR
1, 2, 6
4
4
1, 2
6
1, 2
6
1, 2, 6
1, 2
6
1, 2
6
1, 2
6
4
4.7
1.4
5
0
2.4
385
395
115
120
5.3
2.6
445
445
145
145
-4.7
200
200
180
180
4.1
4.3
2
V
V
V
mA
mA
mA
mA
V
mA
mA
mA
mA
W
W
mV/V
bits
-5.3
-5
165
170
135
145
3.4
3.6
0.5
8
V
IN
V
INB
V
IN
V
INB
C
IN
I
IN
R
IN
FPBW
SSBW
4
4
-125
-125
-250
0
125
125
250
mV
mV
mV
mV
4
4
4
4
4
0.5
1.3
1.5
3
10
1
1.5
1.7
3.5
20
pF
µA
MΩ
GHz
GHz
ECL or specified clock input
power level in dBm
4
V
IL
V
IH
I
IL
I
IH
-1.1
5
5
DBm into 50
Ω
4
C
CLK
4
-2
4
3
10
3.5
dBm
pF
50
50
-1.5
V
V
µA
µA
Clock input power level into 50
Ω
termination
Clock input power level
Clock input capacitance
Product Specification
5
stm32/stm8
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