TS68952
MODEM TRANSMIT/RECEIVE CLOCK GENERATOR
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INDEPENDANT TRANSMIT AND RECEIVE
CLOCK GENERATORS WITH DIGITAL
PHASE LOCKED LOOPS
TRANSMIT DPLL SYNCHRONIZATION ON
EXTERNAL TERMINAL CLOCK OR INTER-
NAL RECEIVE CLOCK
RECEIVE DPLL SYNCHRONIZATION CON-
TROLLED FROM THE BUS
FOUR EXTERNAL CLOCKS AVAILABLE,
PLESIOCHRONOUS ON TRANSMIT AND
RECEIVE CHANNELS :
- BIT RATE CLOCK
- BAUD RATE CLOCK
- SAMPLING CLOCK
- MULTIPLEXING CLOCK
DIRECT INTERFACE WITH STANDARD MPU
8-BIT BUS
LOW POWER CMOS TECHNOLOGY
AVAILABLE IN DIL OR SURFACE MOUNT
PACKAGE
The TS68952 copes with all the CCITT recommen-
dations from V.22 to V.33 including full-duplex rec-
ommendations. Used in conjunction with the
TS68950 Transmit (Tx) Analog Front-End circuit
and the TS68951 Receive Analog Front-End*, it
provides a very cheap and efficient interface to
digital signal processing functions in high speed
modems.
* The interconnection between the 3 chips of the Modem Analog
Front-end (MAFE) and a DSP is described page 11.
DIP28
(Plastic Package)
ORDER CODE :
TS68952CP
DESCRIPTION
The TS68952 is a Clock Generator circuit designed
to generate all the necessary clocks frequencies
needed by high-speed modems applications.
PIN CONNECTIONS
DIP28
D7
D6
D5
D6
D7
E
R/W
CS0
CS1
RS0
RS1
TO
TxSCLK
DGND
XTAL1
XTAL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D4
PLCC2828
(Plastic Chip Carrier)
ORDER CODE :
TS68952CFN
PLCC28
D5
D4
D3
D2
26
D1
25
24
23
22
21
20
19
18
11
12
13
14
15
16
17
28
D3
D2
D1
E
R/W
4
5
6
7
8
9
10
27
3
2
1
TxCCLK
TxCLK
RxCLK
RxCCLK
RxRCLK
RxMCLK
TxMCLK
68952-01.EPS / 68952-02.EPS
TxCCLK
TxCLK
RxCLK
RxCCLK
RxRCLK
RxMCLK
TxMCLK
V+
TxRCLK
CLK
CS0
CS1
RS0
RS1
TO
TxSCLK
XTAL1
XTAL2
CLK
TxRCLK
DGND
V+
March 1995
1/16
TS68952
PIN FUNCTIONS
Pin N°
25 - 26
27 - 28 - 1
2 -3
4
5
6 -7
8 -9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
D1-D7
E
R/W
CS0-CS1
RS0-RS1
TO
TxSCLK
DGND
XTAL1
XTAL2
CLK
TxRCLK
+
V
TxMCLK
RxMCLK
RxRCLK
RxCCLK
RxCLK
TxCLK
TxCCLK
Function
Data Bus Inputs to Internal Registers (DO is not used)
Enable Input. Data are strobed on the positive transitions of this input.
Read/Write Selection Input. Internal registers can be written when R/W = 0.
Reading mode is only used for Rx analog front-end chip.
Chip Select Inputs. The chip set is selected when CS0 = 0 and CS1 = 1
Register Select Inputs. Used to select address or control registers.
Test Output. Must be left open.
Transmit Synchronizing Clock Input. Normally tied to an external terminal clock.
When this pin is tied to a permanent logical level, transmit DPLL free-runs or can be
synchronized to the receive clock system.
Digital Ground = 0V All digital signals are referenced to this pin.
Crystal Oscillator or Pulse Generator Input
Crystal Oscillator Output
1.44MHz Clock output useful for Tx and Rx analog front-end chips
Transmit Baud Rate Clock Output
Positive Power Supply Voltage = +5V
±5%
Transmit Multiplexing Clock Output
Receive Multiplexing Clock Output
Receive Baud Rade Clock Output
Receive Conversion Clock Output
Receive Bit Rate Clock Output
Transmit Bit Rate Clock Output
Transmit Conversion Clock Output
BLOCK DIAGRAM
TERMINAL CLOCK
TxSCLK
ANALOG FRONT-END
CLK
TxCLK
TxRCLK
TxCCLK
TxMCLK
MUX
R
Tx
DPLL
CLKO
DSP
D1:D7
LOCAL BUS
ADDRESS
REGISTER
ARC
E
R/W
CS0/CS1
RS0/RS1
RxCLK
TS68930/31
or
ST18930/31
CONTROL REGISTERS
RC1 - RC2 - RC7 - RC8
CTRL
RxRCLK
RxCCLK
RxMCLK
MUX
Rx
DPLL
XTAL1
5.76MHz
XTAL2
68952-03.EPS
TS68952
DGND V
+
2/16
68952-01.TBL
TS68952
FUNCTIONAL DESCRIPTION
The TS68952 is a digital circuit that synthesises all
the frequencies required to implement synchro-
nous voice-grade MODEMs from 1200bps to
19200bps. It consists of two clock generators using
Digital Phase Locked Loops (DPLLs). Frequency
programming and DPLL updating can be obtained
through four control registers accessed by indirect
or cyclical addressing (see p 8117).
This circuit is a part of a three chip Modem Analog
Front-End that also includes the TS68950 transmit
analog interface and the TS68951 receive analog
interface.
POWER-UP INITIAL CONDITIONS
Following power-up, the eight transmit and receive
clock outputs are undefined and may deliver any
frequencies. Control registers RC1 and RC2 must
be properly programmed to obtain the requested
operation.
CLOCK GENERATION
Master clock is obtained from either a crystal tied
between XTAL1 and XTAL2 pins or an external
signal connected to the XTAL1 pin ; in this case,
the XTAL2 pin should be left open. Clock frequency
nominal value is 5.76MHz, but 5.12MHz and
5.40MHz frequencies are also specified for particu-
lar applications.
The different transmit (Tx) and receive (Rx) clocks
are obtainedby frequency division inseveral count-
ers and output selection through digital multiplex-
ers. They can be synchronized on external signal
via two independent digital phase locked loops
(DPLL).
TRANSMIT DPLL
As shown Figure 1, the TxDPLL operatesby adding
or subtracting pulses to a 2.88MHz internal clock,
Figure 1 :
DPLL Lead and Lag
INTERNAL
2.88MHz CLOCK
DPLL OUTPUT
LEAD
LAG
68952-04.AI
with a reference frequency that is a submultiple of
the programmed ”rate clock” frequency. This cor-
responds to phase leads or phase lags of about
350ns duration, more precisely, two master clock
periods.
The TxDPLL can be synchronized on an external
terminal clock tied to TxSCLK pin or on the receive
bit clock RxCLK internally generated from the
RxDPLL. It can also free-run without any phase
shift, when the TxSCLK input is tied to a fixed
logical level.
TRANSMIT CLOCKS
The TS68952 delivers four synchronousTx clocks :
- a bit clock, TxCLK, whose frequency equals the
bit rate ot the modem,
- a baud clock, TxRCLK, whose frequency equals
the baud rate of the modem,
- a conversion clock, TxCCLK, that gives the sam-
pling frequency of the Tx converter (also used by
the Rx converter in echo cancelling applications),
- a multiplexing clock, TxMCLK, usable when sev-
eral terminals are multiplexed on a single physical
link.
The frequencies of these four clocks are program-
mable through RC1 and RC2 control registers.
Their cyclical ratio is exactly 1 : 2, except for the
16.8kHz frequency whose cyclical ratio is slightly
modulated around 1 : 2, and their relative phase
locking is ensured without user intervention, by
periodic reset of the counters.
Immediate phasing of these clocks on the synchro-
nizing external TxSCLK or internal RxCLK clock
can be obtained through bit 7 or RC8 register. The
content of this register is automaticallycleared after
phasing completion.
The TS68952 also delivers, on pin CLK, a 1.44MHz
clock that is synchronous with the Tx clock system
and will be used as the main clock to the
TS68950/51 analog interface circuits.
3/16
TS68952
RECEIVE DPLL
RxDPLL phase shifts are performed by addition
and subtraction of pulses from an internal 1.44MHz
clock under the control of RC8 register. Two modes
of operation are provided :
- a coarse phase lag whose amplitude has been
loaded into RC7 register, can be controlledby one
bit of RC8 register. This mode is useful for a fast
synchronization of the RxDPLL. The phase lag is
obtained by suppressing a variable number of
pulses at the input of the counters,
- a fine phase shift with lead or lag amplitude equal
to two master clock periods, can be controlled by
two bits of RC8. This mode correspondsto normal
operation. The phase shifts are obtained by addi-
tion or suppression of pulses as indicated in
Figure 1.
RC8 register is automatically cleared when the
programmed phase shift is completed. Simultane-
ous programming of Tx and Rx control bits of this
register has to be avoided.
RECEIVE CLOCKS
The TS68952 delivers four Rx clocks with the same
nominal frequency values as their Tx counterparts :
- a bit clock RxCLK,
- a baud clock RxRCLK,
- a conversion clock RxCCLK,
- a multiplexing clock RxMCLK.
The Rx and Tx output clocks are plesiochronous.
BIT CLOCK FREQUENCY PROGRAMMING
(Tx and Rx)
RC1 Register
D7
HB4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
D6
HB3
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
D5
HB2
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
1
D4
HB1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
D3
HR3
D2
HR2
D1
HR1
19.2
16.8
14.4
12.0
9.6
7.2
6.4
6.0
4.8
3.2
2.4
1.2
0.6
0.6
0.6
68952-02.TBL
Output Frequency (kHz)
F
Q
= 5.76MHz
F
Q
= 5.40MHz
F
Q
= 5.12MHz
6.4
3.0
0.6
F
Q
= crystal oscillator frequency.
4/16
TS68952
RATE CLOCK FREQUENCY PROGRAMMING
(Tx and Rx)
RC1 Register
D7
HB4
D6
HB3
D5
HB2
D4
HB1
D3
HR3
0
0
0
0
1
1
1
1
D2
HR2
0
0
1
1
0
0
1
1
D1
HR1
0
1
0
1
0
1
0
1
2.4
2.0*
1.6**
1.2
0.6
0.6
0.6
68952-03.TBL
Output Frequency (kHz)
F
Q
= 5.76 MHz
F
Q
= 5.40 MHz
F
Q
= 5.12 MHz
2.133
1.5
0.6
Note :
Phase shift frequency of TxDPLL is 600Hz excepted for (*) 1000Hz and for (**) 800Hz.
CONVERSION CLOCK FREQUENCY PROGRAMMING
(Tx and Rx)
RC2 Register
D7
HM3
D6
HM2
D5
HM1
D4
HS2
0
0
1
1
D3
HS1
0
1
0
1
D2
HTHR
D1
—
9.6
8.0
7.2
7.2
Output Frequency (kHz)
F
Q
= 5.76MHz
F
Q
= 5.40MHz
9.0
7.5
F
Q
= 5.12MHz
8.533
68952-04.TBL
MULTIPLEXING CLOCK FREQUENCY PROGRAMMING
(Tx and Rx)
RC2 Register
D7
HM3
0
0
0
0
1
1
1
1
D6
HM2
0
0
1
1
0
0
1
1
D5
HM1
0
1
0
1
0
1
0
1
D4
HS2
D3
HS1
D2
HTHR
D1
—
Output Frequency (kHz)
F
Q
= 5.76 MHz
1440
288
12
9.6
7.2
2.4
1.2
68952-05.TBL
4.8
Tx SYNCHRONIZATION SIGNAL PROGRAMMING
RC2 Register
D7
HM3
D6
HM2
D5
HM1
D4
HS2
D3
HS1
D2
HTHR
0
1
Note :1.TxDPLL
free-runs if there is no transition on this input.
D1
—
Synchronization Signal
RxCLK
TxSCLK (note 1)
68952-06.TBL
5/16
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