HIGH-SPEED BiCMOS
ECL STATIC RAM
64K (64K x 1-BIT) SRAM
Integrated Device Technology, Inc.
IDT10490
IDT100490
IDT101490
FEATURES:
•
•
•
•
•
•
•
•
65,536 x 1-bit organization
Address access time: 7/8/10/12/15 ns
Low power dissipation: 500mW (typ.)
Guaranteed Output Hold time
Fully compatible with ECL logic levels
Separate data input and output
JEDEC standard through-hole package
Guaranteed-performance die available for MCMs/hybrids
DESCRIPTION:
The IDT10490, IDT100490 and IDT101490 are 65,536-bit
high-speed BiCMOS ECL static random access memories
organized as 64K x 1, with separate data input and output. All
I/Os are fully compatible with ECL levels.
These devices are part of a family of asynchronous one-bit-
wide ECL SRAMs. The device has been configured to follow
the standard ECL SRAM JEDEC pinout. Because they are
manufactured in BiCMOS technology, power dissipation is
greatly reduced over equivalent bipolar devices.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
DECODER
16,384-BIT
MEMORY
ARRAY
V
CC
V
EE
A
15
D
0
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
WE
CS
2757 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1992
Integrated Device Technology, Inc.
SEPTEMBER 1992
DSC-8001/4
1
IDT10490, IDT100490, IDT101490
HIGH-SPEED BiCMOS ECL STATIC RAM 64K (64K x 1-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
Q
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
NC
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
D
0
CS
WE
NC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
PACKAGES
Q
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
V
EE
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
D
0
CS
WE
A
15
A
14
A
13
A
12
A
11
A
10
A
9
2757 drw 04a
300-Mil-Wde
CERDIP PACKAGE
D22-1
300-Mil-Wide
PLASTIC SOJ PACKAGE
SO24-4
2757 drw 04b
CERDIP
Top View
2759 drw 02a
SOJ
Top View
2759 drw 02b
PIN DESCRIPTIONS
Symbol
A
0
through A
15
D
0
Q
0
WE
CS
V
EE
V
CC
Pin Name
Address Inputs
Data Input
Data Output
Write Enable Input
Chip Select Input (Internal pull down)
More Negative Supply Voltage
Less Negative Supply Voltage
2757 tbl 01
Hi-Rel Die
For Hybrid and MCM
Applications
2757 drw 05
LOGIC SYMBOL
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
DIP
Symbol
C
IN
C
OUT
Parameter
Input
Capacitance
Output
Capacitance
Typ.
4
6
Max.
—
—
SOJ
Typ.
3
3
Max.
—
—
Unit
pF
pF
2757 tbl 02
TRUTH TABLE
(1)
CS
H
L
L
WE
X
H
L
DataOUT
L
RAM Data
L
Function
Deselected
Read
Write
2757 tbl 03
NOTE:
1. H=High, L=Low, X=Don’t Care
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
D
0
Q
0
CS
WE
2757 drw 06
2
IDT10490, IDT100490, IDT101490
HIGH-SPEED BiCMOS ECL STATIC RAM 64K (64K x 1-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
Rating
Terminal Voltage
With Respect to GND
Operating
Temperature
10K
100K
101K
Ceramic
Plastic
Value
+0.5 to –7.0
0 to +75
0 to +85
0 to +75
–55 to +125
–65 to +150
–55 to +125
1.5
–50
Unit
V
°C
AC/DC ELECTRICAL OPERATING RANGES
I/O
10K
100K
V
EE
–5.2V
±
5%
–4.5V
±
5%
T
A
0 to +75°C, air flow exceeding 2 m/sec
0 to +85°C, air flow exceeding 2 m/sec
2757 tbl 05
101K –4.75V to –5.46V 0 to +75°C, air flow exceeding 2 m/sec
T
BIAS
T
STG
P
T
I
OUT
Temperature Under Bias
Storage
Temperatuure
°C
°C
W
mA
Power Dissipation
DC Output Current
(Output High)
NOTE:
2757 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (1)
10K
Symbol
V
OH
Parameter
Output HIGH Voltage
(V
IN
= V
IH(Max)
or V
IL(Min)
)
Output LOW Voltage
(V
IN
= V
IH(Max)
or V
IL(Min)
)
Output Threshold HIGH Voltage
(V
IN
= V
IH(Min)
or V
IL(Max)
)
Output Threshold LOW Voltage
(V
IN
= V
IH(Min)
or V
IL(Max)
)
Input HIGH Voltage
(Guaranteed Input Voltage
High for All Inputs)
Input LOW Voltage
(Guaranteed Input Voltage
Low for All Inputs)
Input HIGH Current
CS
V
IN
= V
IH(Max)
Others
Input LOW Current
V
IN
= V
IL(Min)
CS
Others
Supply Current
Min.
–1000
–960
–900
–1870
–1850
–1830
–1020
–980
–920
—
—
—
–1145
–1105
–1045
–1870
–1850
–1830
—
—
0.5
–50
–100
Max.
–840
–810
–720
–1665
–1650
–1625
—
—
—
–1645
–1630
–1605
–840
–810
–720
–1490
–1475
–1450
220
110
170
90
—
TA
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
—
—
—
—
—
100K/101K
Min.
–1025
Max.
–880
Unit
mV
V
OL
–1810
–1620
mV
V
OHC
–1035
—
mV
V
OLC
—
–1610
mV
V
IH
–1165
–880
mV
V
IL
–1810
–1475
mV
I
IH
—
—
0.5
–50
–90 (100K)
–100 (101K)
220
110
170
90
—
—
µA
µA
µA
µA
mA
I
IL
I
EE
NOTE:
1. RL = 50Ω to –2V, air flow exceeding 2m/sec.
2757 tbl 05
3
IDT10490, IDT100490, IDT101490
HIGH-SPEED BiCMOS ECL STATIC RAM 64K (64K x 1-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC TEST LOAD CONDITION
V
CC
(GND)
AC TEST INPUT PULSE
–0.9V
80%
20%
DATA
OUT
–1.7V
C*
50
Ω
t
R
t
R
= t
F
= 1.5ns typ.
t
F
2757 drw 08
0.01
µ
F
V
EE
–2.0V
2757 drw 07
NOTE:
1. All timing measurements are referenced to 50% input level.
NOTE:
1. *Includes probe and jig capacitance.
C <5pF (7ns speed grades)
C <30pF (all other speed grades)
RISE/FALL TIME
Symbol
tR
tF
Parameter
Output Rise Time
Output Fall Time
Min.
—
—
Typ.
1.5
1.5
Max.
—
—
Unit
ns
ns
2757 tbl 06
FUNCTIONAL DESCRIPTION
The IDT10490, IDT100490, and IDT101490 BiCEMOS
ECL static RAMs provide high speed with low power dissipa-
tion typical of BiCMOS ECL. These devices follow the
conventional pinout and functionality for 64Kx1 ECL SRAMs.
WRITE TIMING
To write data to the device, a Write Pulse need be formed
on the Write Enable input (WE) to control the write to the
SRAM array.
While CS and ADDR must be set-up when WE goes low,
DataIN can settle after the falling edge of WE, giving the data
path extra margin. Data is written to the memory cell at the end
of the Write Pulse, and addresses and Chip Select must be
held after the rising edge of the Write Pulse to ensure satisfac-
tory completion of the cycle.
DataOUT is disabled (held low) during the Write Cycle. If
CS is held low (active) and addresses remain unchanged, the
Data OUT pin will output the written data after "Write Recovery
time" (t
WR
).
Because of the very short Write Pulse requirement, these
devices can be cycled as quickly for Writes as for Reads.
READ TIMING
The read timing on these asynchronous devices is straight-
forward. DataOUT is held low until the device is selected by
Chip Select (CS). The Address (ADDR) settles and data
appears on the output after time t
AA
. Note that DataOUT is
held for a short time (t
OH
) after the address begins to change
for the next access, then ambiguous data is on the bus until a
new time t
AA
.
4
IDT10490, IDT100490, IDT101490
HIGH-SPEED BiCMOS ECL STATIC RAM 64K (64K x 1-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Over the AC Operating Range)
S7
Symbol
t
ACS
t
RCS
t
AA
t
OH
Parameter
(1)
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Data Hold from Address
Change
NOTE:
1. Input and Output reference level is 50% point of waveform.
2. Output load capacitance, C < 5pF (7ns speed grade only), see "AC Test Load Condition" on previous page.
2757 tbl 07
S8
S10,12,15
Min. Max. Min. Max. Min. Max. Unit
—
—
—
2.5
2.5
2.5
7.0
—
—
—
—
3.0
3.0
3.0
8.0
—
—
—
—
3.5
5.0
5.0
10.0
—
ns
ns
ns
ns
Read Cycle
READ CYCLE GATED BY CHIP SELECT (1, 2)
CS
t
ACS
DATA
OUT
2757 drw 09
t
RCS
READ CYCLE GATED BY ADDRESS (1, 3)
ADDR
t
AA
t
OH
DATA
OUT
2757 drw 10
NOTE:
1. WE is HIGH for read cycle.
2. Address valid prior to or minimum of tAA-tACS before CS active.
3. CS active prior to or minimum tAA-tACS after address valid.
5
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