Envoy
™
-CE4 Device
SPI-3 to Ethernet Controller
TXC-06885
DATA SHEET
PRODUCT PREVIEW
FEATURES
• 4 Configurable Media Access Controllers (MACs)
• Each MAC is configurable as 8 Fast Ethernet ports
(10/100 Mbits/s) or 2 Fast Ethernet ports with extended
buffers or 1 Gigabit Ethernet port (10/100/1000 Mbits/s)
• SPI-3 interface configurable in Link or PHY layer mode,
operating at 125 MHz
• Support for Jumbo frames (9600 Bytes) and Super
Jumbo frames (12000 Bytes)
• Full and Half Duplex (CSMA/CD) operation (Half
Duplex only supported for Fast Ethernet)
• Programmable SPI-3 burst size from 64 to 1024 bytes
• Frame integrity verification (FCS and Frame length
checks) and generation
• Packet statistics and Performance monitoring support
for RMON per port
• PAUSE frame flow control for Full Duplex mode
• “Raise Carrier” flow control for Half Duplex mode
• Programmable high and low FIFO watermarks for flow
control trigger
• Automatic PAUSE frame generation and termination
• Filtering of PAUSE frames in Ethernet Ingress or
Egress
• Port aggregation from Ethernet to SPI-3, using routing
tag encapsulation
• 8/16 bit Intel/Motorola host processor interface,
operating at 33/66 MHz
• IEEE 1149.1 JTAG support
• 580-lead plastic ball grid array (PBGA) package,
27 mm x 27 mm
DESCRIPTION
The Envoy
™
-CE4 is the next generation of powerful Ethernet to
SPI-3 Controllers for carrier-class networks. The Envoy-CE4
incorporates four configurable Media Access Controllers
(MACs). Each MAC can be configured as a single Gigabit
Ethernet (10/100/1000 Mbits/s) or dual Fast Ethernet with
extended buffers or octal Fast Ethernet (10/100 Mbits/s)
interface and is programmable for either full-duplex or half-
duplex operation. The Envoy-CE4 supports Super Jumbo (12
KBytes) packets on both Fast Ethernet and Gigabit Ethernet
interfaces.
The Envoy-CE4 is designed to interface directly with SPI-3
compliant devices, such as network processors. The support
for master mode on the SPI-3 allows glueless interface with
standard SPI-3 based GFP/VCAT framers and mappers. On
the Ethernet side, the Envoy-CE4 interfaces directly with
standard Fast Ethernet and Gigabit Ethernet PHY/SerDes
devices via the SMII and GMII. The Envoy-CE4 incorporates
on-chip buffering to promote high performance without
congestion or loss of data and provides backpressure support
on both the Ethernet and SPI-3 interfaces.
APPLICATIONS
• Metro Edge Routers and Switches
• Ethernet over SONET/SDH Multi-Service Provisioning
Platforms (MSPPs)
• IP DSLAMs
• 3G Wireless Base Stations
• 3G Radio Network Controllers (RNCs)
• Multi-Service Access Platforms (MSAPs)
8/16 bit @ 33/66MHz
NETWORK SIDE
Host Interface
SWITCH SIDE
System
Interface
Ethernet
(SMII/MII/GMII)
32 10/100
4 10/100/1000
Envoy-CE4
Network
Interface
SPI-3 to
Ethernet Controller
TXC-06885
SPI-3
8/16/32 bit @ 104/125 MHz
MMII
JTAG
U.S. and/or foreign patents issued or pending
Copyright © 2004 TranSwitch Corporation
Envoy and EtherMap are trademarks of TranSwitch Corporation
PHAST, TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
PRODUCT PREVIEW
TXC-06885-MB, Ed. 2
May 2004
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, Connecticut 06484
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com
•
USA
PRODUCT PREVIEW
information documents contain information on
products in their formative or design phase of development. Features,
characteristic data and other specifications are subject to change. Contact
TranSwitch Marketing for current information on this product.
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-CE4
TXC-06885
TABLE OF CONTENTS
Section
Page
List of Figures .................................................................................................................................... 3
Features............................................................................................................................................. 4
Envoy-CE4 Configurations........................................................................................................... 4
Media Access Controller (MAC)................................................................................................... 4
Serial Media Independent Interface (SMII) .................................................................................. 5
Ethernet interface port description for different modes ................................................................ 6
Management Media Independent Interface (MMII)...................................................................... 6
Ingress & Egress Buffering Mechanism....................................................................................... 6
SPI-3 Interface ............................................................................................................................. 7
Microprocessor Interface ............................................................................................................. 7
JTAG Interface............................................................................................................................. 7
Envoy-CE4 Normal vs. Aggregate Mode ..................................................................................... 7
Block Diagram ................................................................................................................................... 8
Block Diagram Description .............................................................................................................. 11
Envoy-CE4 Interfaces ................................................................................................................ 11
Lead Diagram .................................................................................................................................. 17
Lead Descriptions ............................................................................................................................ 18
Absolute Maximum Ratings and Environmental Limitations............................................................ 37
Thermal Characteristics................................................................................................................... 37
Power Requirements ....................................................................................................................... 37
Input, Output and Input/Output Parameters..................................................................................... 38
Timing Characteristics ..................................................................................................................... 40
OIF SPI-3 ................................................................................................................................... 45
Operation ......................................................................................................................................... 54
SMII/GMII to SPI-3 Flow Functional Operation.......................................................................... 54
SPI-3 to SMII/GMII Flow Functional Operation.......................................................................... 57
Ethernet Half Duplex........................................................................................................................ 61
Ethernet Full Duplex Flow Control ............................................................................................. 62
Port Aggregation ........................................................................................................................ 63
Configuration and Status Memory Map Information ........................................................................ 64
Application Examples .................................................................................................................... 101
Package Information...................................................................................................................... 102
Ordering Information...................................................................................................................... 103
Related Products ........................................................................................................................... 103
Standards Documentation Sources ............................................................................................... 104
List of Data Sheet Changes........................................................................................................... 106
Please note that TranSwitch provides documentation for all of its products. Current editions of many documents
are available from the Products page of the TranSwitch Web site at
www.transwitch.com.
Customers who are using
a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive
relevant updated and supplemental documentation as it is issued. They should also contact the Applications
Engineering Department to ensure that they are provided with the latest available information about the product,
especially before undertaking development of new designs incorporating the product.
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PRODUCT PREVIEW
Gigabit Media Independent Interface (GMII) & Media Independent Interface (MII) ..................... 5
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-CE4
TXC-06885
LIST OF FIGURES
Figure
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Page
Envoy-CE4 Configurable MAC Block Diagram......................................................... 8
Envoy-CE4 Block Diagram ....................................................................................... 8
1000 Mbps (GMII) Only Interface Connection .......................................................... 9
10/100 Mbps (MII) Only Interface Connection .......................................................... 9
Microprocessor Interface: Motorola 8-bit Write Cycle............................................. 13
Microprocessor Interface: Motorola 8-bit Read Cycle............................................. 13
Microprocessor Interface: Motorola 16-bit Write Cycle........................................... 14
Microprocessor Interface: Motorola 16-bit Read Cycle........................................... 14
Microprocessor Interface: Intel 8-bit Write Cycle .................................................... 15
Microprocessor Interface: Intel 8-bit Read Cycle.................................................... 15
Microprocessor Interface: Intel 16-bit Write Cycle .................................................. 16
Microprocessor Interface: Intel 16-bit Read Cycle.................................................. 16
Envoy-CE4 TXC-06885 Lead Diagram .................................................................. 17
SMII Sync In/Out Timing......................................................................................... 40
SMII Transmit Interface Timing .............................................................................. 40
SMII Receive Interface Timing ............................................................................... 41
GMII Transmit Interface Timing Using
GmTXCLK..................................................
42
GMII Receive Interface Timing Using
GmRXCLK
.................................................. 43
MII Interface Timing ................................................................................................ 44
SPI-3 Data Input Interface Timing ......................................................................... 45
SPI-3 Data Output Interface Timing ....................................................................... 46
Boundary Scan Timing Diagram............................................................................. 47
Motorola MPC860 Mode Write Cycle ..................................................................... 48
Motorola MPC860 Mode Read Cycle ..................................................................... 50
Intel Mode Write Cycle ........................................................................................... 52
Intel Mode Read Cycle ........................................................................................... 53
Flexible Architecture for Ethernet over SONET/SDH & Router Application.......... 101
Envoy-CE4 TXC-06885 Package Diagram........................................................... 102
1000/100/10 Mbps (GMII/MII) Interface Connection .............................................. 10
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PRODUCT PREVIEW
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-CE4
TXC-06885
FEATURES
Envoy-CE4
CONFIGURATIONS
The Envoy-CE4 has 4 Configurable Media Access Controllers:
- Configurable MAC A services ports 0 to 7
- Configurable MAC B services ports 8 to 15
- Configurable MAC C services ports 16 to 23
- Configurable MAC D services ports 24 to 31
Each MAC can be configured as:
• 8 Fast Ethernet ports with 7.75 KBytes of Ingress buffering and 3.1 KBytes of Egress buffering per port
supporting 10/100 Mbits/s data rates via SMII.
OR
• 1 Gigabit Ethernet port with 62 KBytes of Ingress buffering and 24.8 KBytes of Egress buffering per port
supporting 10/100/1000 Mbits/s data rates via GMII/MII.
OR
• 2 Fast Ethernet ports with 31 KBytes of Ingress buffering and 12.4 KBytes of Egress buffering per port
supporting 10/100 Mbits/s data rates via SMII. (Extended SMII Mode)
Possible Envoy-CE4 Configurations:
- 32 Fast Ethernet Ports
- 4 Gigabit Ethernet Ports
- 16 Fast Ethernet and 2 Gigabit Ethernet Ports
- 24 Fast Ethernet Ports and 1 Gigabit Ethernet Port
- 8 Fast Ethernet Ports (Extended SMII Mode) with larger buffers (31 KBytes of Ingress Buffering and
12.4 KBytes of Egress Buffering per port).
MEDIA ACCESS CONTROLLER (MAC)
The main features supported by each Configurable MAC are:
• Compliant to IEEE 802.3, 802.3i, 802.3u, 802.3x, 802.3z
• Full Duplex and Half Duplex (CSMA/CD) operation per configurable MAC
• Connection to standard 10/100 Mbit/s Fast Ethernet PHY devices via SMII interface
• Connection to Multi-rate 10/100/1000 Mbits/s Gigabit Ethernet PHY devices via GMII/MII interface
• Frame Integrity Verification (FCS and length checks)
• Errored Frames can be configured to be filtered
• Programmable Inter-Packet Gap (IPG) between Ethernet frames
• Programmable maximum frame length
• Minimum frame size = 64 bytes
• Maximum frame size = 12 KBytes
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PRODUCT PREVIEW
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-CE4
TXC-06885
• Support for VLAN tagged frame transmission
• Programmable High and Low FIFO watermarks for space and frame/chunk availability generation
• MAC control sublayer provides support for control frames including PAUSE frames
• Automatic PAUSE Frame Generation and Termination
• 62 KByte ingress FIFO per Configurable MAC
• 24.8 KByte egress FIFO per Configurable MAC
• Packet statistics and performance monitoring support for Remote Network Monitoring (RMON)
SERIAL MEDIA INDEPENDENT INTERFACE (SMII)
The Serial Media Independent Interface (SMII) is capable of operating at 10/100 Mbits/s mixed mode. The
SMII is configurable to operate in either Full Duplex or Half Duplex mode.
Control and Data are transported across the TX and RX signals in 10 bit segments. The segments are syn-
chronized using the SYNC signal. From the 10 bits, 2 bits are control and the other 8 bits are data. In 100
Mbits/s mode, every 10 bit segment transfers a new byte of data. In 10 Mbits/s mode, each 10 bit segment is
repeated ten times. Please refer to the SMII specification for further details.
Each SMII port is comprised of:
• Two serial data signals (Tx and Rx) per port
• 125 MHz reference clock signal (Clock) per Configurable MAC
• Synchronization signal (SYNC) per Configurable MAC
GIGABIT MEDIA INDEPENDENT INTERFACE (GMII) & MEDIA INDEPENDENT INTERFACE (MII)
The GMII interface of the Envoy-CE4 is capable of operating at 1 Gbit/s. When configured in MII mode, the
interface is capable of operating in 10/100 Mbits/s. The GMII/MII ports allow the Envoy-CE4 to connect to
Multi-rate Gigabit Ethernet PHY devices.
When configured as GMII, each port is comprised of:
• Two data buses, Transmit and Receive, each 8 bits wide
• Two clock signals, 1 per direction
• The transmit clock is an output and the receive clock is an input
• Two network status signals (Rx Error and Tx Error)
• Two control signals (Rx Data Valid and Tx Enable)
• All signals are synchronous to the clock
When configured as MII, each port is comprised of:
• Two data buses, Transmit and Receive, each 4 bits wide
• Uses LSNibble of the GMII bus
• Two clock signals, 1 per direction
• Both the transmit and receive clocks are inputs to the Envoy-CE4
• Four Status signals (Rx Data Valid, Tx Enable, Carrier sense, and Collision detect)
Note: The GMII signal pins are muxed with the SMII signal pins.
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PRODUCT PREVIEW
• Far end switch side loopback for diagnostic capability
DSP 与 ARM 处理器
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