74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 300MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC74B
74AC74M
DESCRIPTION
The 74AC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
transition of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
et
l
o
P
e
od
r
s)
t(
uc
T&R
74AC74MTR
74AC74TTR
April 2001
1/12
74AC74
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 13
2, 12
3, 11
SYMBOL
1CLR, 2CLR
1D, 2D
1CK, 2CK
NAME AND FUNCTION
Asynchronous Reset -
Direct Input
Data Inputs
Clock Input
(LOW to HIGH, Edge
Triggered)
Asynchronous Set - Direct
Input
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
Ground (0V)
Positive Supply Voltage
4, 10
5, 9
6, 8
7
14
1PR, 2PR
1Q, 2Q
1Q, 2Q
GND
V
CC
TRUTH TABLE
INPUTS
CLR
L
H
L
H
H
H
X : Don’t Care
OUTPUTS
D
X
X
X
L
H
X
CK
X
X
X
Q
L
H
H
L
Q
PR
H
L
L
H
H
H
LOGIC DIAGRAM
O
so
b
te
le
r
P
uc
od
s)
t(
b
-O
so
Q
n
H
et
l
P
e
H
L
Q
n
H
L
H
od
r
s)
t(
uc
FUNCTION
CLEAR
PRESET
NO CHANGE
This logic diagram has not be used to estimate propagation delays
2/12
74AC74
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
200
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
Parameter
Value
2 to 6
0 to V
CC
1) V
IN
from 30% to 70% of V
CC
O
so
b
te
le
r
P
uc
od
s)
t(
so
b
-O
te
le
r
P
0 to V
CC
8
-55 to 125
od
s)
t(
uc
Unit
V
V
V
°C
ns/V
3/12
74AC74
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Low Level Output
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
I
I
CC
I
OLD
I
OHD
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
5.5
5.5
5.5
V
O
= 0.1 V or
V
CC
-0.1V
V
O
= 0.1 V or
V
CC
-0.1V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-50
µA
I
O
=-12 mA
I
O
=-24 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=50
µA
I
O
=50
µA
I
O
=12 mA
I
O
=24 mA
I
O
=24 mA
V
I
= V
CC
or GND
V
I
= V
CC
or GND
2.9
4.4
5.4
2.56
3.86
4.86
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
T
A
= 25°C
Min.
2.1
3.15
3.85
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
Max.
Value
-40 to 85°C
Min.
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.9
1.35
1.65
2.9
4.4
5.4
Max.
-55 to 125°C
Min.
2.1
3.15
3.85
0.9
1.35
1.65
Max.
V
Unit
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IL
V
V
OH
V
OLD
= 1.65 V max
V
OHD
= 3.85 V min
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
l
o
te
e
±
0.1
2
r
P
0.44
0.44
0.44
±
1
20
75
-75
od
s)
t(
uc
3.7
4.7
0.1
0.1
0.1
0.5
0.5
0.5
±
1
40
50
-50
µA
µA
mA
mA
V
2.4
V
4/12
74AC74
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
5.0
4.0
4.0
3.0
2.0
2.0
1.0
1.0
100
140
T
A
= 25°C
Min.
Typ.
7.0
5.0
6.0
4.5
1.5
1.5
-0.2
-0.2
0.2
0.2
-1.0
-0.7
300
300
Max.
14.0
10.0
12.0
9.5
7.0
5.0
4.0
3.0
3.0
3.0
1.0
1.0
90
Value
-40 to 85°C
Min.
Max.
16.0
10.5
13.5
10.5
7.0
5.0
4.0
3.0
3.0
ns
-55 to 125°C
Min.
Max.
17.5
12.0
14.0
10.5
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
t
W
Pulse Width HIGH
or LOW, CK or PR
or CLR
t
s
Setup Time D to CK
HIGH or LOW
t
h
t
REM
f
MAX
Hold Time D to CK
HIGH or LOW
Removal Time
PR or CLR to CK
Maximum Clock
Frequency
ns
130
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Flip-Flop)
O
so
b
te
le
r
P
uc
od
s)
t(
so
b
-O
Min.
3
35
te
le
Max.
r
P
od
ct
u
1.0
1.0
90
130
3.0
s)
(
ns
ns
MHz
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
Unit
T
A
= 25°C
Typ.
f
IN
= 10MHz
5/12
嵌入式系统
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