Product Specification
PE4259
Product Description
The PE4259 UltraCMOS
®
RF switch is designed to
cover a broad range of applications from 10 MHz
through 3000 MHz. This reflective switch integrates
on-board CMOS control logic with a low voltage
CMOS-compatible control interface, and can be
controlled using either single-pin or complementary
control inputs. Using a nominal +3-volt power supply
voltage, a typical input 1dB compression point of
+33.5 dBm can be achieved.
The PE4259 is manufactured on Peregrine’s
UltraCMOS process, a patented variation of silicon-
on-insulator (SOI) technology on a sapphire
substrate, offering the performance of GaAs with the
economy and integration of conventional CMOS.
SPDT High Power UltraCMOS
®
10 MHz–3.0 GHz RF Switch
Features
Single-pin or complementary CMOS
logic control inputs
Low insertion loss:
0.35 dB @ 1000 MHz
0.5 dB @ 2000 MHz
Isolation of 30 dB @ 1000 MHz
High ESD tolerance of 2 kV HBM
Typical input 1 dB compression point
of +33.5 dBm
1.8V minimum power supply voltage
Ultra-small SC-70 package
Figure 1. Functional Diagram
RFC
ESD
Figure 2. Package Type SC-70
6‐lead SC‐70
RF1
ESD
ESD
RF2
CMOS
Control
Driver
CTRL CTRL or V
DD
DOC-02109
Document No. DOC-03694-3
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©2005-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 10
PE4259
Product Specification
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3V
(Z
S
= Z
L
= 50Ω )
Parameter
Operation frequency
1
Insertion loss
3
Isolation
Return loss
3
‘ON’ switching time
‘OFF’ switching time
Video feedthrough
2
1000 MHz @ 2.3–3.3V
1000 MHz @ 1.8–2.3V
2500 MHz @ 2.3–3.3V
2500 MHz @ 1.8–2.3V
1000 MHz, 20 dBm input power
31.5
29.5
28.5
28
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
50% CTRL to 0.1 dB of final value, 1 GHz
50% CTRL to 25 dB isolation, 1 GHz
29
19
21
24
Condition
Minimum
10
0.35
0.50
30
20
22
27
1.50
1.50
15
33.5
30.5
30.5
29
55
Typical
Maximum
3000
0.45
0.60
Unit
MHz
dB
dB
dB
dB
dB
dB
us
us
mV
pp
dBm
dBm
dBm
dBm
dBm
Input 1dB compression point
Input IP3
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50Ω test
set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
3. A tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. See
Figure 6
for
details.
©2005-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 10
Document No. DOC-03694-3
│
UltraCMOS
®
RFIC Solutions
PE4259
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
Parameter/Condition
Power supply voltage
Voltage on any DC input
Storage temperature
range
Operating temperature
range
Input power (50Ω)
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
ESD Voltage (MM,
JEDEC, JESD22-A114-B)
Min
–0.3
–0.3
–65
–40
Max
4.0
V
DD
+
0.3
150
85
+34*
2000
100
Unit
V
V
°C
°C
dBm
V
V
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
Pin Name
RF1*
GND
RF2
1
CTRL
RFC
1
RF port 1.
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF port 2.
Switch control input, CMOS logic level.
RF common.
This pin supports two interface options:
Single-pin control mode.
A nominal 3-volt
supply connection is required.
6
CTRL
or
V
DD
Complementary-pin control mode.
A
complementary CMOS control signal to
CTRL is supplied to this pin. Bypassing
on this pin is not required in this mode.
Description
V
ESD
Note: * To maintain optimum device performance, do not exceed Max P
IN
at
desired operating frequency (see
Figure 4).
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Figure 4. Maximum Input Power
Note: * All RF pins must be DC blocked with an external series capacitor or
held at 0 VDC.
Table 3. Operating Ranges
Parameter
V
DD
Power supply voltage
I
DD
Power supply current
(V
DD
= 3V, V
CNTL
= 3V)
Control voltage high
Control voltage low
0.7x V
DD
0.3x V
DD
Min
1.8
Typ
3.0
9
Max
3.3
20
Unit
V
µA
V
V
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE4259 in
the SC70 package is MSL1.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
©2005-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 10
Switching Frequency
The PE4259 has a maximum 25 kHz switching rate.
Document No. DOC-03694-3
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PE4259
Product Specification
Table 5. Single-pin Control Logic Truth Table
Control Voltages
Pin 6 (V
DD
) = V
DD
Pin 4 (CTRL) = High
Pin 6 (V
DD
) = V
DD
Pin 4 (CTRL) = Low
Signal Path
RFC to RF1
RFC to RF2
Control Logic Input
The PE4259 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode
enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection on
pin 6 (V
DD
). This mode of operation reduces the
number of control lines required and simplifies the
switch control interface typically derived from a
CMOS
Processor
I/O port.
Complementary-pin control mode
allows the
switch to operate using complementary control
pins CTRL and
CTRL
(pins 4 and 6), that can be
directly driven by +3-volt CMOS logic or a suitable
Processor
I/O port. This enables the PE4259 to
be used as a potential alternate source for SPDT
RF switch products used in positive control
voltage mode and operating within the PE4259
operating limits.
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages
Pin 6 (CTRL or V
DD
) = Low
Pin 4 (CTRL) = High
Pin 6 (CTRL or V
DD
) = High
Pin 4 (CTRL) = Low
Signal Path
RFC to RF1
RFC to RF2
Thermal Data
Psi-JT (
JT
), junction top-of-package, is a thermal
metric to estimate junction temperature of a de-
vice on the customer application PCB (JEDEC
JESD51-2).
JT
= (T
J
– T
T
)/P
Where
parameter, °C/W
JT
= junction-to-top of package characterization
T
J
= die junction temperature, °C
T
T
= package temperature (top surface, in the
center), °C
P = power dissipated by device, Watts
Table 7. Thermal Data
Parameter
Maximum junction temperature, T
JMAX
(RF input power, CW = 31.5 dBm, +85 °C
ambient)
Typ
99
37
104
Unit
°C
°C/W
°C/W
JT
JA
, junction-to-ambient thermal resistance
©2005-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 10
Document No. DOC-03694-3
│
UltraCMOS
®
RFIC Solutions
PE4259
Product Specification
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE4259. The
RF common port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RF1 and RF2 are connected through 50Ω
transmission lines via SMA connectors J2 and J3,
respectively. A through 50Ω transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and
ε
r
of 4.4.
J6 and J7 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device V
DD
or
CTRL
input. J7-1 is connected
to the device CTRL input.
Figure 5. Evaluation Board Layout
DOC-02396
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