REJ09B0186-0300O
16
H8S/2643 Group,
H8S/2643F-ZTAT
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
Rev. 3.00
Revision Date: Jan 11, 2005
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
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whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
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contained therein.
Rev. 3.00 Jan 11, 2005 page ii of liv
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the operation
of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
Rev. 3.00 Jan 11, 2005 page iii of liv
Configuration of this Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
Precautions in Relation to this Product
Configuration of this Manual
Overview
Table of Contents
Summary
Description of Functional Modules
• CPU and System-Control Modules
• On-chip Peripheral Modules
The configuration of the functional description of each module differs according to the module.
However, the generic style includes the following items:
i) Features
ii) I/O pins
iii) Description of Registers
iv) Description of Operation
v) Usage: Points for Caution
When designing an application system that includes this LSI, take the points for caution into
account. Each section includes points for caution in relation to the descriptions given, and points
for caution in usage are given, as required, as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
• Product-type codes and external dimensions
•
Major revisions or addenda in this version of the manual (only for revised versions)
The history of revisions is a summary of sections that have been revised and sections that have
been added to earlier versions. This does not include all of the revised contents. For details,
confirm by referring to the main description of this manual.
10. Appendix/Appendices
Rev. 3.00 Jan 11, 2005 page iv of liv
Preface
The H8S/2643 Group is a group of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*) and masked ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial
communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also
possible to incorporate an on-chip PC bus interface (IIC) as an option.
In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling
high-speed data transfer without CPU intervention.
Use of the H8S/2643 Group enables easy implementation of compact, high-performance systems
capable of processing large volumes of data.
This manual describes the hardware of the H8S/2643 Group. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology, Corp.
Rev. 3.00 Jan 11, 2005 page v of liv
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