REJ09B0133-0200
8
7643 Group
User's Manual
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 7600 SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 2.00
Revision date: Aug 28, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, pro-
grams, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, pro-
grams and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers con-
tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis-
tributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by vari-
ous means, including the Renesas Technology Corp. Semiconductor home page (http://
www.renesas.com).
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa-
tion as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil-
ity or other loss resulting from the information contained herein.
Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at
stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology
Corp. product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Renesas Technology Corp. is necessary to reprint or repro-
duce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be im-
ported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
Please contact Renesas Technology Corp. for further details on these materials or the
products contained therein.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
q
CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
q
CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
q
CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the notes, and the list of registers.
½For
the mask ROM confirmation form, the ROM programming confirmation form, and the mark
specifications, refer to the “Renesas Technology” Homepage (http://www.renesas.com/en/rom).
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0
0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B
16
]
B
0
1
2
3
4
5
6
7
Stack page selection bit
Name
Processor mode bits
b1 b0
Function
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
At reset
R W
0
0
0
0
0
1
½
½
✕
✕
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
Main clock (X
IN
-X
OUT
) stop bit
Internal system clock selection bit
0 : Operating
1 : Stopped
0 : X
IN
-X
OUT
selected
1 : X
CIN
-X
COUT
selected
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1:
. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
½.
......Contents determined by option at reset release
Note 2:
Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, write-
only and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read
disabled
W......Write
..... Write enabled
✕......
Write disabled
3. Supplementation
For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com).
Table of contents
7643 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2
FEATURES ......................................................................................................................................... 2
APPLICATION ................................................................................................................................... 2
PIN CONFIGURATION (TOP VIEW) .............................................................................................. 3
FUNCTIONAL BLOCK DIAGRAM (Package: PRQP0080GB-A) ............................................... 4
PIN DESCRIPTION ........................................................................................................................... 5
PART NUMBERING .......................................................................................................................... 7
GROUP EXPANSION ....................................................................................................................... 8
Memory Type
Memory Size
Memory Expansion ...................................................................................................................... 8
Packages ...................................................................................................................................... 8
FUNCTIONAL DESCRIPTION ......................................................................................................... 9
CENTRAL PROCESSING UNIT (CPU) .................................................................................... 9
MEMORY .................................................................................................................................... 13
I/O PORTS ................................................................................................................................. 15
INTERRUPTS ............................................................................................................................. 21
TIMERS ...................................................................................................................................... 25
SERIAL I/O ................................................................................................................................. 27
UART .......................................................................................................................................... 31
DMAC .......................................................................................................................................... 37
USB FUNCTION ........................................................................................................................ 42
FREQUENCY SYNTHESIZER (PLL) ...................................................................................... 57
RESET CIRCUIT ....................................................................................................................... 59
CLOCK GENERATING CIRCUIT ............................................................................................ 61
PROCESSOR MODE ................................................................................................................ 65
FLASH MEMORY MODE ............................................................................................................... 71
NOTES ON PROGRAMMING ........................................................................................................ 98
USAGE NOTES ............................................................................................................................. 101
ROM ORDERING METHOD ........................................................................................................ 102
FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 103
CHAPTER 2 APPLICATION
2.1 I/O port ........................................................................................................................................ 2
2.1.1 Memory map ...................................................................................................................... 2
2.1.2 Related registers ............................................................................................................... 3
2.1.3 Key-on wake-up interrupt application example ............................................................. 7
2.1.4 Terminate unused pins ..................................................................................................... 9
2.1.5 Notes on I/O port ............................................................................................................ 10
2.1.6 Termination of unused pins ........................................................................................... 11
2.2 Timer .......................................................................................................................................... 12
2.2.1 Memory map .................................................................................................................... 12
2.2.2 Related registers ............................................................................................................. 13
2.2.3 Timer application examples ........................................................................................... 16
2.2.4 Notes on timer ................................................................................................................. 22
Rev.2.00 Aug 28, 2006
REJ09B0133-0200
page 1 of 12
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