HD49306AF
CMOS 9-Bit A/D Converter
Description
The HD49306AF is a high-speed, low-power
monolithic CMOS 9-bit A/D converter LSI.
Features
•
•
•
•
•
Resolution: 9 bits (with overflow)
Power supply voltage: +5.0 V, unitary
Output codes: binary/gray, selectable
Digital output: 3-stateTTL/CMOS compatible
Sleep mode provided (low-power waiting mode)
Pin Arrangement
FP- 48
NC
D1
D0
NC
DV
SS
OE
CLK
NC
DV
DD
GRY
SLP
NC
48 47 46 45 44 43 42 41 40 39 38 37
NC
NC
D2
D3
D4
NC
D5
D6
D7
D8
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
OF
DV
DD
AV
SS
AV
SS
AV
DD
AV
DD
VRTin
VRT
NC
NC
36
35
34
33
32
31
30
29
28
27
26
25
NC
AV
DD
AV
DD
AV
SS
AV
SS
V
IN
NC
VRB
VR3
VR2
VR1
NC
(Top View)
1
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HD49306AF
Pin Description
Pin No.
1, 2
3 to 5
6
7 to 9
10
11 to 14
15
16
17, 18
19, 20
21
Symbol
NC
D2 to D4
NC
D5 to D7
D8
NC
OF
DV
DD
AV
SS
AV
DD
VRTin
Function
Unused
Digital output
Unused
Digital output
Digital output (MSB)
Unused
Digital output (overflow)
Digital power supply (+5 V)
Connect this pin in common with AV
DD
external to the IC.
Analog ground (0 V)
Analog power supply (5 V)
Reference voltage op-amp input (high side: +3 V or 0 V)
When the internal op-amp is used, input +3 V to this pin.
When unused, connect to AV
SS
.
Reference voltage input (high side: +3 V)
When the internal op-amp is used, insert both a 0.1 µF ceramic capacitor
and an over 10 µF chenmical capacitor between this pin and AV
SS
.
When the internal op-amp is not used, apply +3.0 V to this pin.
Unused
Reference voltage intermediate taps.
Insert 0.1 µF capacitors between these pins and AV
SS
.
Reference voltage input (low side: 0 V)
Apply a 0 V reference voltage, or connect to AV
SS
.
Unused
Analog signal input (0 to +3 V)
Analog ground (0 V)
Analog power supply (+5 V)
Unused
Sleep mode control input
H: Sleep mode
L: Normal operating mode
Output code selection
H: Gray code
L: Binary code
Digital power supply (+5 V)
Connect this pin in common with AV
DD
external to the IC.
Unused
Conversion clock input (TTL or CMOS)
22
VRT
23 to 25
26 to 28
29
30
31
32, 33
34, 35
36 to 37
38
NC
VR1 to VR3
VRB
NC
V
IN
AV
SS
AV
DD
NC
SLP
39
GRY
40
41
42
DV
DD
NC
CLK
2
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HD49306AF
Pin Description
(cont)
Pin No.
43
Symbol
OE
Function
Digital output enable
H: High impedance
L: Normal operating mode
Digital ground (0 V)
Connect this pin in common with AV
SS
external to the IC.
Unused
Digital output (LSB)
Digital output
Unused
44
45
46
47
48
DV
SS
NC
D0
D1
NC
Block Diagram
VRTin
21
CLK
42
VRT 22
VR1 26
VR2 27
VR3 28
VRB 29
Reference voltage
generation resistor
network
Upper
comparator
(5 bits)
15 OF
Encoder
Output latch circuits
10 D8
9
8
7
5
4
3
D7
D6
D5
D4
D3
D2
Lower
comparator (4 bits)
Data com-
pensation
circuit
Encoder
Code
selection
circuit
47 D1
46 D0
31
V
IN
38
SLP
39
GRY
43
OE
3
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HD49306AF
Absolute Maximum Ratings
(Ta = 25°C)
Item
Power supply voltage
Input signal
Reference pin voltage
Digital input voltage
Reference pin voltage difference
Operating temperature
Storage temperature
Symbol
V
DD(max)
V
IN(max)
V
REF(max)
V
I(max)
V
RT
– V
RB
T
opr
T
stg
Rated Value
6.0
–0.3 to V
DD
+ 0.3
–0.3 to V
DD
+ 0.3
–0.3 to V
DD
+ 0.3
3.1
0 to +70
–55 to +125
Units
V
V
V
V
V
°C
°C
Notes: 1. V
DD
refers to both AV
DD
and DV
DD
.
2. Connect AV
DD
and DV
DD
to a common point outside the IC. If AV
DD
and DV
DD
are separated by
a noise filter, make sure that their voltages differ by less than 0.3 V or power up, and by less than
0.1 V during operation.
3. Connect AV
SS
and DV
SS
to a common point outside the IC.
Electrical Characteristics
(Unless otherwise specified, V
DD
= 5.0 V, V
RT
= 3.0 V, V
RB
= 0.0 V, Ta = 25°C, and the internal op-amp is unused.)
Item
Resolution
Symbol
RES
Min
9
4.75
—
300
–400
4
—
Typ
9
5.00
20
480
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
9
5.25
26
—
400
—
0.4
30
V
DD
0.4
V
DD
0.8
50
—
50
—
50
Units Measurement Conditions
bit
V
mA
Ω
µA
V
V
mV
V
V
V
V
µA
µA
µA
µA
µA
V
IH
= V
DD
V
IL
= 0 V
OE
= V
DD
, V
OH
= V
DD
OE
= V
DD
, V
OL
= 0 V
VRTin = 3 V
f
CLK
= 15 MHz
f
IN
= 1 kHz sine wave
Resistance between
V
RT
and V
RB
V
IN
: 0 to 3 V, f
CLK
= 15 MHz
I
OH
= –4 mA
I
OL
= 4 mA
VRTin = 3.0 V
(When the op-amp is used)
Power supply voltage range V
DD
Power supply current
Reference resistance
Analog input current
Digital output voltage
I
DD
R
REF
I
IN
V
OH
V
OL
Op-amp offset
Digital input voltage (SLP)
VRTin-VRT –30
V
IH(SLP)
V
IL(SLP)
V
DD
– 0.3
0
2
0
—
–50
—
–50
–50
Digital input voltage
(other than SLP)
Digital input current
V
IH
V
IL
I
IH
I
IL
Digital output current
I
OZH
I
OZL
Op-amp input current
I
OP
4
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HD49306AF
Electrical Characteristics
(Unless otherwise specified, V
DD
= 5.0 V, V
RT
= 3.0 V, V
RB
= 0.0 V, Ta = 25°C, and the internal op-amp is unused.) (cont)
Item
Maximum conversion
speed
Minimum conversion
speed
Minimum clock pulse width
Symbol
f
CLK(max)
f
CLK(min)
t
WH(min)
t
WL(min)
Maximum clock pulse width
t
WH(max)
t
WL(max)
Digital output delay time
Digital output hold time
Digital output enable time
t
PD
t
HOLD
t
ZH
t
ZL
Digital output disable time
t
HZ
t
LZ
Analog signal read-in time
Integration linearity
Differentiation linearity
t
AP
INL
DNL
Min
15
—
—
—
1
1
—
10
—
—
—
—
–5
—
–0.7
Typ
—
—
—
—
—
—
—
—
25
25
25
25
6
2
—
Max
—
0.5
30
30
—
—
40
—
40
40
40
40
10
5.5
+0.7
Units Measurement Conditions
MHz *1
MHz
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
LSBpp f
CLK
= 15 MHz
LSB
Load capacitance = 10 pF
*1
Note: 1. With the change in input voltage between conversions on each clock 2.2 V or less.
Timing Chart
• Conversion timing
Analog input
(V
IN
)
Conversion
clock
(CLK)
1.4 V
t
AP
N
N+1
N+2
N+3
N+4
t
WH
t
WL
Digital output
(D0 to D8, OF)
N–4
N–3
N–2
N–1
N
t
PD
t
HOLD
5
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