IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
IDT74ALVCH16901
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.50mm pitch TSSOP package
Extended commercial range of -40°C to +85°C
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses
in either direction.
The ALVCH16901 features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA)
inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and
ERRB)
outputs for checking parity. The direction of data flow is controlled by
OEAB
and
OEBA.
When
SEL
is low, the parity functions are enabled. When
SEL
is high, the parity functions are disabled and the device acts as an 18-bit
registered transceiver.
The ALVCH16901 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16901 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
Drive Features for ALVCH16901:
– High Output Drivers: ±24mA
– Suitable for heavy loads
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
LEAB
1
CLKENAB
2
CLKENAB
2
1
32
3
30
2
CLKAB
OEAB
35
OEBA
1
A
1
-
1
A
8
1
APAR
1
ERRB
2
A
1
-
2
A
8
2
APAR
2
ERRB
28
36
5
61
18
A-Port
Parity
Generate
and
Check
B Data
18-Bit
Storage
18
Q
A
B-Port
Parity
Generate
and
Check
A Data
18
29
60
4
1
B
1
-
1
B
8
1
BPAR
1
ERRA
2
B
1
-
2
A
8
37
2
BPAR
2
ERRA
18
Q
B
18-Bit
Storage
ODD/EVEN
SEL
34
31
62
CLKBA
1
CLKENBA
2
CLKENBA
2
64
33
63
LEBA
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
JUNE 2000
DSC-4582/-
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
CLKENAB
ABSOLUTE MAXIMUM RATING
64
63
62
61
60
59
58
57
56
55
54
53
52
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Symbol
V
TERM(2)
1
CLKENBA
LEA B
CLKAB
1
ERRA
1
APA R
LEB A
CLKBA
1
ERRB
1
BPA R
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
GND
1
A
1
1
A
2
1
A
3
GND
1
B
1
1
B
2
1
B
3
V
CC
1
A
4
1
A
5
1
A
6
V
CC
1
B
4
1
B
5
1
B
6
GND
1
A
7
1
A
8
2
A
1
2
A
2
SO64-1 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
GND
1
B
7
1
B
8
2
B
1
2
B
2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
GND
2
A
3
2
A
4
2
A
5
GND
2
B
3
2
B
4
2
B
5
PIN ENABLE
Pin Names
OEAB
OEBA
LEAB
LEBA
xCLKENAB
xCLKENBA
CLKAB
CLKBA
xERRA
xERRB
xAPAR
xBPAR
ODD/EVEN
SEL
xAx
Unit
pF
pF
pF
NEW16link
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B 9-bit Clock Enables
B-to-A 9-bit Clock Enables
A-to-B Clock Input
B-to-A Clock Input
A Error-Signal Outputs
B Error-Signal Outputs
A Port Parities
B Port Parities
Parity Select Input
Parity Enables
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
V
CC
2
A
6
2
A
7
2
A
8
V
CC
2
B
6
2
B
7
2
B
8
GND
2
APA R
2
ERRA
GND
2
BPA R
2
ERRB
OEAB
SEL
2
CLKENAB
OEBA
ODD/EVEN
2
CLKENBA
SSOP/
33
TSSOP/TVSOP
TOP VIEW
o
CAPACITANCE
(T
A
= +25 C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
xBx
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
NOTE:
1. As applicable to the device type.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE
Inputs
CLKENAB
X
X
X
H
L
L
L
L
OEAB
H
L
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
L
(1, 2)
Outputs
CLKAB
X
X
X
X
↑
↑
L
H
xAx
X
L
H
X
L
H
X
X
xBx
Z
L
H
B
0(3)
L
H
B
0(3)
B
0(4)
PARITY ENABLE
Inputs
SEL
L
L
L
L
H
H
H
H
OEBA OEAB
H
L
H
L
L
L
H
H
L
H
H
L
L
H
L
H
Operation or Function
Parity is checked on port A and is generated on port B.
Parity is checked on port B and is generated on port A.
Parity is checked on port B and port A.
Parity is generated on port A and B if device is in FF
mode.
Parity functions are
disabled; device acts as
a standard 18-bit
registered transceiver.
Q
A
data to B, Q
B
data to A
Q
B
data to A
Q
A
data to B
Isolation
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA,
LEBA, and
CLKENBA.
3. Output level before the indicated steady-state conditions were
established.
4. Output level before the indicated steady-state conditions were
established, provided that CLKAB was LOW before LEAB went
LOW.
PARITY
SEL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OEBA
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
OEAB
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
ODD/EVEN
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
H
Inputs
∑
OF INPUTS
A1−A8 = H
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
Outputs
∑
OF INPUTS
B1−B8 = H
N/A
N/A
N/A
N/A
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
xAPAR
L
L
H
H
N/A
N/A
N/A
N/A
L
L
H
H
N/A
N/A
N/A
N/A
L
L
H
H
L
L
H
H
N/A
N/A
xBPAR
N/A
N/A
N/A
N/A
L
L
H
H
N/A
N/A
N/A
N/A
L
L
H
H
L
L
H
H
L
L
H
H
N/A
N/A
xAPAR
N/A
N/A
N/A
N/A
L
H
L
H
N/A
N/A
N/A
N/A
H
L
H
L
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PE
(1)
PO
(2)
xERRA
H
L
L
H
Z
Z
Z
Z
L
H
H
L
Z
Z
Z
Z
H
L
L
H
L
H
H
L
Z
Z
xBPAR
L
H
L
H
N/A
N/A
N/A
N/A
H
L
H
L
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PE
(1)
PO
(2)
xERRB
Z
Z
Z
Z
H
L
L
H
Z
Z
Z
Z
L
H
H
L
H
L
L
H
L
H
H
L
Z
Z
NOTES:
1. Parity output is set to the level so that the specific bus side is set to even parity.
2. Parity output is set to the level so that the specific bus side is set to odd parity.
3
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
4
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
22
5
V
CC
= 3.3V ± 0.3V
Typical
27
8
Unit
pF
pF
5
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