IDT74ALVCH16831
3.3V CMOS 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 1-BIT TO 4-BIT
ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in TVSOP package
IDT74ALVCH16831
FEATURES:
DESCRIPTION:
This 1-bit to 4-bit address register/driver is built using advanced dual
metal CMOS technology. This device is ideal for use in applications in which
a single address bus is driving four separate memory locations. The
ALVCH16831 can be used as a buffer or a register, depending on the logic
level of the select (SEL) input.
When
SEL
is logic high, the device is in the buffer mode. The outputs follow
the inputs and are controlled by the two output-enable (OE) controls. Each
OE
controls two groups of nine outputs. When SEL is logic low, the device
is in the register mode. The register is an edge-triggered D-type flip-flop.
On the positive transition of the clock (CLK) input, data set up at the A inputs
is stored in the internal registers.
OE
controls operate the same as in buffer
mode.
The ALVCH16831 has been designed with a ±24mA ouput driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16831 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
•
•
•
•
Memory subsystems
PC Motherboards and servers
Workstations
Telecommunications
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©1999 Integrated Device Technology, Inc.
R
FO E
C N
R O
O
N M T
EW M
EN
D
ES DE
IG D
N
S
OE
1
20
5
OE
2
21
1
Y
1
CLK
19
4
CLK
2
Y
1
2
A
1
8
3
Y
1
D
Q
1
0
1
4
Y
1
SEL
22
TO EIGHT OTHER CHANNELS
OCTOBER 1999
DSC-4495/1
IDT74ALVCH16831
3.3V CMOS 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
4
Y
1
3
Y
1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
Y
2
2
Y
2
Unit
V
V
°C
mA
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
GND
2
Y
1
1
Y
1
GND
3
Y
2
4
Y
2
V
CC
NC
A
1
GND
NC
A
2
GND
NC
A
3
V
CC
NC
A
4
GND
CLK
OE
1
OE
2
SEL
GND
A
5
A
6
V
CC
A
7
NC
GND
A
8
NC
GND
A
9
NC
V
CC
4
Y
9
3
Y
9
V
CC
1
Y
3
2
Y
3
GND
3
Y
3
4
Y
3
GND
1
Y
4
2
Y
4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
V
CC
3
Y
4
4
Y
4
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
GND
1
Y
5
2
Y
5
3
Y
5
4
Y
5
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
OEx
CLK
SEL
Ax
xYx
NC
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Select Input
Data Inputs
(1)
3-State Outputs
No Internal Connection
GND
1
Y
6
2
Y
6
V
CC
3
Y
6
4
Y
6
GND
1
Y
7
2
Y
7
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
GND
3
Y
7
4
Y
7
FUNCTION TABLE
(1)
Inputs
OEx
H
L
L
L
L
SEL
X
H
H
L
H
CLK
X
X
X
↑
↑
Ax
X
L
H
L
H
Outputs
xYx
Z
L
H
L
H
V
CC
1
Y
8
2
Y
8
GND
2
Y
9
1
Y
9
GND
3
Y
8
4
Y
8
TVSOP
TOP VIEW
2
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
IDT74ALVCH16831
3.3V CMOS 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74ALVCH16831
3.3V CMOS 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Register/Driver Outputs enabled
Power Dissipation Capacitance per Register/Driver Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
119
22
V
CC
= 3.3V ± 0.3V
Typical
132
25
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
SU
t
H
t
SK(O)
Propagation Delay
Ax to xYx
Propagation Delay
SEL
to xYx
Propagation Delay
CLK to xYx
Output Enable Time
OEx
to xYx
Output Disable Time
OEx
to xYx
Pulse Duration, CLK HIGH or LOW
Set-up Time, Ax data before CLK↑
Hold Time, Ax data after CLK↑
Output Skew
(2)
3.3
2
0.7
—
—
—
—
—
3.3
2
0.5
—
—
—
—
—
3.3
1.6
1.1
—
—
—
—
500
ns
ns
ns
ps
1.4
5.5
—
4.7
1.6
4.5
ns
1.1
5.1
—
5
1.2
4.3
ns
1.1
4.5
—
4.4
1.5
3.9
ns
1.3
5.2
—
5.2
1.7
4.4
ns
Parameter
Min.
150
1.2
Max.
—
4
V
CC
= 2.7V
Min.
150
—
Max.
—
4.1
V
CC
= 3.3V ± 0.3V
Min.
150
1.6
Max.
—
3.6
Unit
ns
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16831
3.3V CMOS 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
CC
500Ω
Pulse
Generator
(1, 2)
V
LOAD
Open
GND
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
ALVC Link
V
IN
D.U.T.
R
T
V
OUT
500Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
OUTPUT 2
t
PLH2
t
PHL2
V
T
ALVC Link
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
Pulse Width
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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