IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH162260:
– High Output Drivers: ± 24mA (A port)
– Balanced Output Drivers: ± 12mA (B port)
–
–
–
IDT74ALVCH162260
separate data paths must be multiplexed onto, or demultiplexed from,
a single data path. Typical applications include multiplexing and/or
demultiplexing address and data information in microprocessor or bus-
interface applications. This device also is useful in memory-interleav-
ing applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output-enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The OE1B
and OE2B control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input is
high, the latch is transparent. When the latch-enable input goes low, the
data present at the inputs is latched and remains latched until the latch-
enable input is returned high.
The ALVCH162260 has series resistors in the device output structure
of the “B” port which will significantly reduce line noise when used with
light loads. This driver has been designed to drive ±12mA at the
designated threshold levels. The “A” port has a ± 24mA driver.
The ALVCH162260 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
DESCRIPTION:
This multiplexed D-type latch is built using advanced dual metal CMOS
technology. The ALVCH162260 is used in applications in which two
Functional Block Diagram
OE1B
LEA1B
29
30
A-1B
LATCH
12
1B
1:12
2
LE1B
12
28
1B-A
LATCH
12
12
SEL
1
OEA
M
U
X
1
A
1:12
12
0
12
12
27
LE2B
2B-A
LATCH
12
55
LEA2B
56
A-2B
LATCH
2B
1:12
12
OE2B
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4628/1
IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA
LE1B
2
B
3
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
O E2B
LEA 2B
2
B
4
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
S O 5 6 -1
S O 5 6 -2
S O 5 6 -3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
2
B
2
2
B
1
GND
2
B
5
2
B
6
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
V
CC
A
1
A
2
A
3
GND
A
4
A
5
A
6
A
7
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1
B
1
1
B
2
V
CC
2
B
7
2
B
8
2
B
9
GND
2
B
10
2
B
11
2
B
12
1
B
12
1
B
11
1
B
10
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
GND
1
B
9
1
B
8
1
B
7
V
CC
1
B
6
1
B
5
NOTE:
1. As applicable to the device type.
GND
1
B
3
GND
1
B
4
LE2B
SEL
LEA 1B
O E1B
FUNCTION TABLES
(1)
Inputs
1
Bx
2
Bx
B TO A (OE1B = OE2B = H)
Output
LE2B
X
X
X
H
H
L
X
OEA
L
L
L
L
L
L
H
Ax
H
L
A
0(2)
H
L
A
0(2)
Z
SEL
H
H
H
L
L
L
X
LE1B
H
H
L
X
X
X
X
SSOP/
TSSOP/TVSOP
TOP VIEW
H
L
X
X
X
X
X
X
X
X
H
L
X
X
2
IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLES (cont'd)
A TO B (OEA = H)
Inputs
Ax
H
L
H
L
H
L
X
X
X
X
X
LEA1B
H
H
H
H
L
L
L
X
X
X
X
LEA2B
H
H
L
L
H
H
L
X
X
X
X
OE1B
L
L
L
L
L
L
L
H
L
H
L
OE2B
L
L
L
L
L
L
L
H
H
L
L
H
L
H
L
1
B
0(2)
1
B
0(2)
1
B
0(2)
Outputs
1
Bx
2
Bx
H
L
2
B
0(2)
2
B
0(2)
H
L
2
B
0(2)
Z
Active
Z
Active
Z
Z
Active
Active
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. A
0
, xB
0
= Level of A or xB before the indicated steady-state input conditions were established.
PIN DESCRIPTION
Pin Names
Ax
1
Bx
2
Bx
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
(1)
(1)
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
(1)
LEA1B
LEA2B
LE1B
LE2B
SEL
OEA
OE1B
OE2B
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched
on the HIGH to LOW transition of LEA1B.
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-port is latched
on the HIGH to LOW transition of LEA2B.
Latch Enable Input for 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched
on the HIGH to LOW transition of LE1B.
Latch Enable Input for 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched
on the HIGH to LOW transition of LE2B.
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL
enables data transfer from 2B Port to A Port.
Output Enable for A Port (Active LOW).
Output Enable for 1B Port (Active LOW).
Output Enable for 2B Port (Active LOW).
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs, outputs, or I/Os.
3
IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40° C to +85° C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
4
IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
V
CC
= 2.7V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
NEW16link
Unit
V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
5
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