FASTPULSE MediaCAT
HIGH SPEED LAN TRANSCEIVERS
Twisted pair transceiver kit for TP-FDDI,
100BaseTX and ATM 155 Mbps
Matched integrated circuit and magnetic
module
Flexible, cost-effective frontend solution
Part
Number
PE-95000
PE-95010
PE-68517L
Description
Transceiver IC
Transceiver IC
Magnetic Module
Magnetic Module
Application
100Base-TX & TP-FDDI
ATM 155 Mbps
100Base-TX
ATM 155 Mbps
TP-FDDI
100Base-TX
General Description
FASTPULSE
MediaCAT
(Chip
And Transformer)
is a transceiver
component kit which enables the design of high performance, low-
cost frontends for high speed LAN products.
MediaCAT
consists of
a monolithic twisted pair transceiver which implements the core
Transmit/Receive signal processing and a matched magnetic mod-
ule which provides the wideband transformer coupling and EMI
filtering. The
MediaCAT
transceiver forms the analog interface
between the digital PHY controller and the twisted pair cable
(UTP-5 or STP). The matched nature of the devices and proven
performance reduces the design effort and risk of implementing
100 Mbps+ frontends.
Employing
FASTPULSE
technology, the
MediaCAT
transceiver
PE-95000/10 incorporates transmit conditioning, receiver adaptive
equalization to compensate for cable losses and baseline restora-
tion to correct DC drifts in receiver datastream. The two key
encode/decode schemes which the ICs can implement are MLT3
(PE-95000) and Binary (PE-95010). MLT3 is a three level coding
scheme which is used in TP-FDDI and 100Base-TX applications to
support 125 Mbaud (100 Mbps) data transmission over 100 m of
shielded (STP) or unshielded twisted pair (UTP) Category 5 cable
(2 pair). Binary coding (NRZ) is used principaly for
ATM 155 Mbps applications, to support 155 Mbps transmission
over 100 m STP or UTP Category 5 cable. The device has
a high degree of flexibility to allow it to be used in various standard
applications and to enable performance tailoring for customer
specific requirements.
The PE-68517L is an integrated magnetic module device designed
for TP-FDDI, 10/100Base-TX and ATM155 Mbps applcations. It
provides a balanced, wideband transformer with dual common
mode chokes to minimize EMI emissions. The device charac-
teristics are tuned to the
MediaCAT
transceiver resulting in an
optimized device pair. For certain 10/100 Mbps applications the
PE-69016 provides the 10 Mbps and 100 Mbps magnetic interface
with integrated passive mixer.
PE-69016
Features
•
•
•
•
High performance twisted pair transceiver solution
Flexible frontend kit for 100Base-TX, ATM 155 & TP-FDDI
Full compliance with PMD standards IEEE, ANSI and ATM
Supports 100m of Unshielded Twisted Pair (UTP), Category 5
or Shielded Twisted Pair (STP) cable
MediaCAT IC
•
•
•
•
•
•
•
Integrates
high performance and programmable adaptive
equalizer
Integrates compliant base line wander correction circuitry
Versions for MLT3 and binary operation
Programmable drive current
Direct interface to PHY controllers
EMC optimized design — edge rate control, CMRR
BiCMOS device/PLCC28 package
MediaCAT Magnetics
•
•
•
Integrated transformer/choke device — tuned to MediaCAT IC
Provides TX/RX wide bandwidth isolation and EMI filtering
SMD package for IR reflow compatibility
Applications
•
•
•
•
•
•
•
Network adapter cards (ISA, PCI, VME etc.)
Hubs or concentrators
Motherboards (PC, workstation, industrial)
Bridges, routers, switches
Switch uplink modules
Point to point links (Telecom)
Peripherals: storage, print servers, etc.
MediaCAT
devices meet or exceed the electrical specifications of
the following standards: ANSI X3.263 TP-PMD for TP-FDDI, IEEE
802.3u for Fast Ethernet 100Base-TX and ATM-UNI-PMD STS3c
for ATM 155 Mbps applications.
U.S.A:
TEL 619 674 8100
•
EUROPE:
TEL 44 1483 401700
•
ASIA:
TEL 886 7 821 3141
•
WEB:
http://www.pulseeng.com
1
H335.A (9/97)
FASTPULSE MediaCAT
COFF
Block Diagram
BASELINE
RESTORATION
ZEQ2P
ZEQ2N
ZEQP
ZEQN
REQP
REQN
RDP
DECODER
RXP
ADAPTIVE
EQUALIZER
RXN
RD+
RD-
RX+
RX-
RDN
PHY CONTROLLER
CPEAK
PEAK
DETECTER
CT
EQGAIN
CT
SDP
SIGNAL
DETECT
REFERENCE
CIRCUIT
EQREF
CT
CMT
TX+
TX-
CDEL
TDP
ENCODER
TXP
TRANSMIT
AMPLIFIER
TXN
TD+
TD-
TDN
PE-95000 / PE-95010
VDD
ENCSEL
TXREF
VSS
PE-68517L
Functional Description
The transmitter inputs (TDP, TDN) receive a differential data
stream at pseudo ECL levels from the physical layer controller.
The signal is fed to an encoder which converts the binary data
(NRZI) to MLT3 format, or passes it through unencoded, (NRZ-
NRZ) depending on the setting of the ENCSEL pin (see Fig. 2).
The signal is then fed to a current output driver whose maximum
signal amplitude is controlled by an external resistor at TXREF.
The differential current output at TXP, TXN drives the cable via
the transformer/Choke module. The pull-up resistors for transmit
outputs effectively form the line termination for the cable (Zcable/2
since transformer is 1:1). The wide band transformers provide the
high voltage isolation and exhibit a high inductance in order to
minimize signal droop in presence of DC bias, i.e baseline shift.
The dual common mode chokes and further decoupling schemes
ensure minimal EMI emissions.
In the receive channel, the incoming differential signal from the
cable passes through the transformer/choke before being termi-
nated and fed to the RXP/RXN inputs of the IC. The termination is
performed by the pull-up resistors (Zcable/2). The core function of
the receiver circuitry is the adaptive equalizer which compensates
for the cable losses.
This attenuation and phase distortion will vary with frequency and
cable length. These cable characteristics are defined by EIA/TIA
568 standard — Figure 1 shows typical UTP-5 cable attenuation
curves which incorporate “real world” connector and punch-down
block contributions, as well as typical equalizer response curve to
compensate for these losses. The equalizer transfer function of
PE-95000/10 is fully controlled by external components resulting
in a low cost and flexible architecture. The application circuit
section details the filters required (at REQP/REQPN,
ZEPQ/ZEQPN and ZEQP2/ZEQPN2 pins) for standard applica-
tions over standard twisted pair cable. The effect of the external
filter networks on the signal is varied from zero to full compensa-
tion by a feedback loop which senses the incoming amplitude
(with peak detector) and optimizes the applied equalization.
The equalized signal is fed to the decoding circuit which converts
the analog signal to a digital PECL datastream, converting from
MLT3 or NRZ waveforms as selected by the ENCSEL pin. The
baseline restoration loop compensates for baseline wander i.e DC
drifts in incoming signal which may occur due to data pattern
dependent DC shifts and the inherent low frequency bandwidth of
the channel and AC coupling transformers. If not corrected this
baseline wander effect can cause degradation in signal/noise ratio
and furthermore, result in data errors/link failure. The feedback
loop compares the incoming equalized signal with a reconstructed
reference. The difference is filtered and used to effect low fre-
quency compensation in order to maintain the equalized signal at
the reference level. The filter characteristic is determined by the
external capacitor at COFF. Its value has been chosen to remove
disruptive high frequency components while allowing the circuit to
track baseline changes limited by the time constant of the trans-
formers. The receiver outputs are then driven out by PECL buffers
to be connected to physical layer controller.
The signal detect circuit monitors the gain control to give a reliable
indication of the presence of a valid equalized signal in accor-
dance with the TP-PMD specification.
U.S.A:
TEL 619 674 8100
•
EUROPE:
TEL 44 1483 401700
•
ASIA:
TEL 886 7 821 3141
•
WEB:
http://www.pulseeng.com
H335.A (9/97)
2
FASTPULSE MediaCAT
FIGURE 1
Typical UTP CAT5
Cable Loss Curves
0 dB
25m
50m
-10 dB
75m
Typical Equalizer
Transfer Function
30
25
125m
20
100m
(dB)
15
75m
10
50m
-20 dB
100m
5
0
-5
100KHz
0m
25m
-30 dB
100
KHz
1.0MHz
10MHz
100MHz
500MHz
10
MHz
100 200
MHz MHz
Frequency
FIGURE 2
NRZI-MLT3 Line Coding
Data to be Transmitted (After 4B/5B Encoding and Scrambling)
1
1
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
1
1
1
1
0
Line Bit Clock at the Baud Rate
NRZI Waveform
MLT-3 Waveform
U.S.A:
TEL 619 674 8100
•
EUROPE:
TEL 44 1483 401700
•
ASIA:
TEL 886 7 821 3141
•
WEB:
http://www.pulseeng.com
3
H335.A (9/97)
FASTPULSE MediaCAT
System Application
PHYSICAL CONTROLLER
PMD TRANSCEIVER
MEDIA
CELL
EXTRACTIO
FRAMING
SERIAL TO
PARALLEL
TWISTED
PAIR
ATM 155
CLOCK
RECOVERY
CLOCK
GENERATOR
Transceiver
IC
TD±
CELL
INSERTION
FRAMING
SYNC.
PARALLEL
TO SERIAL
NRZ DATA
(PECL)
PE-95010
MediaCAT
PE-68517L
Magnetic
RD±
Connector
NRZ DATA
(LINE)
TP-FDDI/100BASE-TX
4B/5B
DECODER
DESCRAMBLE
SERIAL TO
PARALLEL
TWISTED
PAIR
CLOCK
GENERATOR
SD+
Transceiver
IC
TD±
4B/5B
CODER
SCRAMBLE
PARALLEL
TO SERIAL
NRZI DATA
(PECL)
PE-95000
MediaCAT
PE-68517L
Magnetic
CLOCK
RECOVERY
RD±
Connector
MLT3 DATA
(LINE)
Switch
4B/5B
DECODER
DESCRAMBLE
SERIAL TO
PARALLEL
TWISTED
PAIR
10/100BASE-TX
CLOCK
GENERATOR
MediaCAT
Transceiver
IC
4B/5B
CODER
SCRAMBLE
PARALLEL
TO SERIAL
PE-95000
PE-68517L
NOTES:
1. Switching can also be performed here.
2. PE-69016 provides 10/100
transformer/choke with passive mixer
10Base-T
Transceiver
10Base-T
Magnetics
MediaCAT
enables implementation of any of the following 100Base-TX product architectures:
1. 100Base-TX only adapters and repeaters.
2. 10/100-TX adapters with separate 10/100 cable connectors.
3. 10/100-TX products which employ 10/100 switching (on primary or secondary of magnetics).
4. 10/100-TX products which employ common magnetic module (PE-69016) with inherent 10/100 mixing. The 10/100 system diagram indicates a
generic switching arrangement.
U.S.A:
TEL 619 674 8100
•
EUROPE:
TEL 44 1483 401700
•
ASIA:
TEL 886 7 821 3141
•
WEB:
http://www.pulseeng.com
H335.A (9/97)
4
Magnetic
Relay
CLOCK
RECOVERY
NOTE 1
Connector
FASTPULSE MediaCAT
Signal
ZEQN
ZEQP
ZEQ2N
ZEQ2P
RDP
RDN
VDDN
CPEAK
SDP
VSSN
CDEL
TDN
TDP
VDDTX
TXP
TXN
ENCSEL
VSSTX
TXREF
EQREF
COFF
EQGAIN
RXP
RXN
VDDR
REQN
REQP
VSSR
Pin # Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Equalizer Network 1 -
(1)
Equalizer Network 1 +
(1)
Equalizer Network 2 -
(2)
Equalizer Network 2+
(2)
Receive Data + (To controller)
Receive Data - (To controller)
Supply Voltage (Receive)
Peak detector capacitor
(3)
Signal Detect +
Ground (Receive)
Signal Detect delay capacitor
(4)
Transmit input - (From Controller)
Transmit input + (From Controller)
Supply Voltage (Transmit)
Transmit Data output + (To cable )
Transmit Data output - (To Cable)
MLT3/Binary mode select
Ground (Transmit)
Transmit Amplitude reference
(6)
Equalizer reference current
(7)
DC offset correction capacitor
(8)
Equalizer gain control
(9)
Receive input + (from cable)
Receive input - (from Cable)
Supply Voltage (Receive)
Equalizer gain resistor -
(10)
Equalizer gain resistor +
(10)
Ground (Receive)
(5)
I/O
I/O
I/O
I/O
I/O
O
O
–
O
O
–
O
I
I
–
O
O
I
–
I
I
O
O
I
I
–
I/O
I/O
–
Type
Voltage
Voltage
Voltage
Voltage
PECL
PECL
Supply
Current
PECL
Supply
Current
PECL
PECL
Supply
Current
Current
CMOS
Supply
Current
Current
Current
Current
Voltage
Voltage
Supply
Voltage
Voltage
Supply
NOTES:
RDP
RDN
VDDN
CPEAK
SDP
VSSN
CDEL
5
6
7
8
9
28
27
26
25
24
23
4
3
2
1
ZEQ2P
ZEQ2N
ZEQP
ZEQN
VSSR
REQP
REQN
Pin Descriptions
PE-95000/10
22
21
20
19
10
12
13
14
15
16
17
11
1. ZEQP/N:
The RC network between these pins sets a
frequency dependent gain which is increased linearly
from zero to maximum as the equalization level
increases from minimum to maximum.
2. ZEQ2P/N:
The RC network between these pins sets
a frequency dependent gain which is increased lin-
early from zero to maximum as the equalization level
increases from its mid point to maximum. This pro-
vides gain boost for longer lengths of cable.
3. CPEAK:
The RC network at CPEAK pin control the
frequency response of the on chip peak detector.
4. CDEL:
The capacitor at CDEL delays assertion of
the SD signal to allow the equalizer to stabilize.
Max assert time (us)=C(
E Q G A I N
)(nF)X40 +
C(
CDEL
)(nF)X25.
5. ENCSEL:
TTL compatible CMOS selection pin of
encode/decode mode. High = Binary, Low = MLT3.
6. TXREF:
Resistor controls the amplitude of the cur-
rent outputs, which determines the transmit signal
voltage amplitude. For the total system (Chip +
Transformer), the resistor value can be determined
as follows: R(
TXREF
) = (20 x Zcable) / Vpp where
Vpp = peak-peak differential amplitude (line output)
(V) Zcable = Characteristic differential cable
impedance
7. EQREF:
The resistor at EQREF pin sets internal ref-
erence currents for the receiver circuitry.
8. COFF:
Capacitor determines time constant of
BLW loop.
9. EQGAIN:
Indicates gain factor of equalizer. The
capacitor at this pin determines the maximum SD
deassert time. Maximum deassert time (us) =
C(
EQGAIN
) (nF) x 20
10. REQP/N:
The resistor at REQP/N sets the minimum
signal gain through the equalizer.
U.S.A:
TEL 619 674 8100
•
EUROPE:
TEL 44 1483 401700
•
ASIA:
TEL 886 7 821 3141
•
WEB:
http://www.pulseeng.com
5
H335.A (9/97)
TDN
TDP
VDDTX
TXP
TXN
ENCSEL
VSSTX
18
VDDR
RXN
RXP
EQGAIN
COFF
EQREF
TXREF
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
