Product Brief
May 2003
TAAD08JU21BCLSU3A-DB (SAR-500)
AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1
Features
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Description
SAR-500
provides a flexible network-interface
solution for next-generation wireless infrastructure
applications in which efficient transport of voice and
data information is critical to guaranteeing network
QoS for the user and transmission efficiency for the
network operator. Constructed using Agere Systems
Inc. 0.16 µm CMOS technology, the chip implements
AAL2 and AAL5 SAR functions.
Support for AAL2 is provided via an AAL/CPS
function that maps/demaps variable-sized CPS
packets to/from ATM-SDU. A total of 512 bidirectional
CIDs are supported. These CIDs can be transported
within a programmable number of VCs per direction.
SAR-500
supports up to 124 AAL2 VCs which may be
allocated between ingress and egress traffic.
Support for high-speed data switching is provided
whereby AAL5 VCs are routed through to the system
interface toward their destinations.
SAR-500
provides
support for up to 2032 bidirectional AAL5 VCs via an
internal context memory.
Communication with
SAR-500
is accomplished
through three primary interfaces:
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System-on-a-chip integrated circuit supports ATM
adaptation process for next-generation wireless
base transmission station (BTS), node B, base sta-
tion controller (BSC), radio network controller
(RCN), and voice gateway applications.
Integrates an ATM adaptation layer 2 (AAL2) seg-
mentation and reassembly (SAR) function for sup-
port of low-speed data or voice traffic per ITU
I.363.2.
Provides AAL5 SAR functionality per ITU I.363.5.
Provides quality of service (QoS) connection identi-
fier (CID) multiplexing per ITU I.366.1.
Integrates on-chip memory to support a combina-
tion of 512 bidirectional AAL2 CIDs or 2032 bidirec-
tional AAL5 VCs.
On-board memory is used for connection manage-
ment and queue data storage. No external memory
is needed.
Software package includes the following:
— Device manager source code (C-based device
manager ready-to-use with host RTOS).
— Firmware for embedded controller (executable
binary).
— Setup file utility to provision
SAR-500.
— API manual available for device manager soft-
ware.
Designed in 0.16 µm, low-power CMOS technology.
3.3 V digital I/O compatibility; 1.5 V core power.
520 enhanced ball-grid array (EBGA) package.
–40
o
C to +85
o
C temperature range.
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The host interface, which is a 32-bit synchronous
slave interface primarily used for configuration and
control of SAR along with transporting OAM and
other management traffic.
The network interface, which is a 16-bit UTOPIA 2
slave interface.
The system interface, which can be configured as a
UTOPIA 2 master interface or a UTOPIA-derived
packet master interface. The system interface sup-
ports both 8-bit and 16-bit data bus widths.
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Applications
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BTS network interface termination
Voice traffic over ATM (VToA) trunking application
Low-speed ATM access
AAL2 cross connect
AAL2 and AAL5 conversion
SAR-500
provides a complete ATM adaptation layer
function, including AAL/CPS mapping functions, AAL2
SSSAR, and AAL2 SSTED. The highly integrated,
flexible architecture results in unified SARing features,
simpler operation, and best-in-class operation with
respect to area, power, and function.
TAAD08JU21BCLSU3A-DB (SAR-500)
AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1
Product Brief
May 2003
Block Diagram
Figure 1 shows SAR-500 's architectural block diagram and protocol stack functional block diagram. As seen in
Figure 1B, SAR-500 provides complete AAL2 and AAL5 SARing functions in a single, highly integrated device. The
AAL engine provides a number of segmentation and reassembly options based on AAL2 and AAL5 standards while
maintaining multiple traffic classes and qualities of service.
ATM ADAPTATION TYPES
DATA SSCS: AAL2 I.366.1
AAL2 CPS: I.363.2
AAL5: I.363.5
4-LEVEL INTRA-VC QOS
256 CIDS/VC
MAXIMUM SUPPORTED BANDWIDTH:
155 Mbits/s
SAR-500
SARatoga-2K
SCHEDULER AND
EN(DE)QUEUE MEMORY
TX
INGRESS
SYSTEM
INTERFACE
ADAPTATION
BLOCK
EGRESS
SYSTEM
INTERFACE
ADAPTATION
BLOCK
RX
NETWORK
INTERFACE
UTOPIA 2
INGRESS CELL
ADAPTATION
BLOCK
SUBPACKET
QUEUE AND
SCHEDULING
BLOCK
EGRESS CELL
ADAPTATION
BLOCK
SYSTEM
INTERFACE
UTOPIA 2
RX
STATISTICS
MANAGER
TX
ARM
®
®
9 CONTROLLER
ARM
9
CONTROLLER
32-bit HOST MICROPROCESSOR INTERFACE
MEMORY
(ARM
EMBEDDED DEVICE CONTROLLER (ARM 9):
9):
!
RESPONSIBLE FOR CONTROL FUNCTIONS AND CONFIGURATION, ON-CHIP RESOURCE MANAGEMENT, AND
COMPILATION OF STATISTICAL INFORMATION FOR PERFORMANCE MONITORING.
!
PROVIDES ALARM CORRELATION AMONG THE BLOCKS FOR FASTER FAULT DETECTION AND ISOLATION.
!
CONTROLLED VIA HIGH-LEVEL, SIMPLE, DEVICE-SPECIFIC COMMANDS ISSUED FROM THE EXTERNAL HOST DEVICE.
!
INTERFACES TO EMBEDDED MEMORIES.
!
CONTAINS PROGRAMMABLE INTERUPT CONTROLLER.
!
CONTAINS WATCHDOG TIMER AND SEVEN ADDITIONAL GENERAL-PURPOSE TIMERS.
A. Architectural Block Diagram
SAR-500
SARatoga-2K
AAL2
DATA
SSTED
SSCS
SSSAR
CPS
ATM
ATM DATA
DATA
SYSTEM OR
NETWORK
INTERFACE
(SIF/NIF)
UTOPIA L2
AAL2 DATA
PAT DAT
-
PATM-DATA
A
M
MA UNIDAT
MAP-UNIDATA
-
P
A
SYSTEM OR
NETWORK
INTERFACE
(SIF/NIF)
UTOPIA L2
MAPPING
AAL2 DATA
ATM
ATM DATA
DATA
CPCS
SAR
NULL
ATM
AAL5 DATA
AAL0 DATA
B. Protocol Stack Functional Block Diagram
Figure 1. Block Diagram of the SAR-500 Device
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Agere Systems Inc.
Product Brief
May 2003
TAAD08JU21BCLSU3A-DB (SAR-500)
AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1
Functional Overview
An ATM-SAP is provided to the AAL layers via the UTOPIA interfaces and associated control logic. The AAL
engine adapts service-specific convergence sublayer (SSCS) packets into ATM cells, supporting both AAL2 and
AAL5 protocols. The AAL engine includes class-of-service multiplexing to enable a single AAL2 VC to transport
connections of different traffic types. Figure 2 shows the ATM adaptation protocols supported by SAR-500 and the
functional representation of the architecture.
USER TRAFFIC
USER TRAFFIC
USER TRAFFIC
USER TRAFFIC
CIRCUIT MODE
DATA SERVICES
VOICEBAND SERVICES
FRAME MODE
DATA SERVICES
IWF/IWF CCS
N x 64 kbits/s
DATA
INBAND
SIGNALING
PCM VOICE COMPRESSED
VOICE
FAX DEMOD
IMPLEMENTED AND SUPPORTED
BY SAR-500
SSCS FOR TRUNKING I.366.2
AAL2 CPS: I.363.2
DATA SSCS
I.366.1
AAL5
I.363.5
ATM LAYER I.361
FROM ATM TRUNKING USING AAL2 FOR NARROWBAND SERVICES: AF-VTOA-0113.000
IMPLEMENTED AND SUPPORTED
BY TAAD08JU2
Figure 2. AAL Functions Supported by SAR-500
The SSCS packet is exchanged with the destination SSCS entity via the system or network interface.
Underlying this system-on-chip implementation is an embedded device controller (EDC) that provides an intelligent
higher-level interface for provisioning and monitoring as well as alarm correlation and statistics gathering. This
higher-level, command-based interface simplifies integration of SAR-500 into end systems by reducing firmware
development efforts.
Egress Direction Data Flow
This section describes the basic operation of SAR-500 as data is received from the network interface (shown on
the left side of Figure 1A) and is processed by SAR-500.
Network Interface
SAR-500 receives cells from a high-speed external PHY/TC framer device and optionally through an ATM layer
(switch), directly to the ATM adaptation layer functions via its network interface (NIF). NIF operates in UT2 slave
mode at up to 50 MHz and supports a 16-bit data bus width.
Agere Systems Inc.
3
TAAD08JU21BCLSU3A-DB (SAR-500)
AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1
Product Brief
May 2003
Functional Overview
(continued)
AAL Engine
The AAL engine receives cells via the network interface. This interface functions as a bus slave. Following AAL
processing, cells or packets are forwarded to their destination via the system interface.
The system interface operates in UT2 master mode at up to 50 MHz and supports 8-bit or 16-bit data data bus
widths. It can also operate in one of the two modes:
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Standard UTOPIA Level 2 (also known as UT2) cell-based MPHY master port.
UTOPIA Level 2 plus Packet-over-SONET (also known as UT2+) MPHY master port.
The AAL engine provides the following types of services, based upon the SSCS entity pertaining to the connection:
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AAL5 reassembly
AAL2/I.366.1 frame reassembly from AAL2 CPS packets
AAL2 demultiplexing (in the case of short CPS packets)
In addition, if the system interface is the cell-based UTOPIA-2 MPHY, the AAL engine may demultiplex CPS packets
from an AAL2 VC into AAL0 cells so that the AAL2 connections can be routed to different destinations within the
system.
The AAL engine provides class-of-service packet scheduling onto the system interface port to distribute service to
different types of traffic via a weighted round-robin scheduler. The AAL engine provides quality-of-service scheduling
onto both system and network interfaces to distribute service to different types of traffic via a hierarchy of schedulers.
The AAL engine may also detect that certain packets (CPS-SDUs or reassembled AAL5 packets) are destined for
the external host device. In this case, the AAL engine transfers the packet to a buffer for access by the external
host via SAR-500 's device manager.
Embedded Device Controller
The embedded device controller (EDC) consists of a microcontroller that manages the general operation of the
other blocks and communicates with an external CPU via the host interface.
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Agere Systems Inc.
Product Brief
May 2003
TAAD08JU21BCLSU3A-DB (SAR-500)
AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1
Functional Overview
(continued)
Ingress Direction Data Flow
The transmit direction refers to data transfer from the system interface/host microprocessor, through SAR-500 ,
and out through the network interface.
SSCS/AAL Layer Interaction
Data links may be received from one of the following two sources:
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System interface
External host microprocessor
Data from the system interface may be formatted as cells or packets. In the case of a cell stream, SAR-500 's AAL
engine may provide AAL0 CPS-packet or AAL2 VC multiplexing; AAL5 cells are passed directly to the ATM layer.
In the case of a packet stream, SAR-500's AAL engine may be programmed to provide the following processing (via
the AAL engine):
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AAL5 segmentation
AAL2/I.366.1 frame SARing into AAL2 CPS packets
AAL2 multiplexing (in the case of short CPS packets)
AAL2 class-of-service scheduling (when multiple traffic classes share a common AAL2 VC)
Data from the external host microprocessor may undergo either of the following:
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AAL5 SARing for an SSCOP service
AAL2 multiplexing as a CPS packet
AAL2/I.366.1 SARing
Agere Systems Inc.
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