Data Sheet, Rev. 1
November 25, 2003
TAAD08JU21BCLUL3A
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
1 Features
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System-on-a-chip integrated circuit supports low-
speed ATM access for next-generation wireless
base transmission station (BTS), base station con-
troller (BSC), node-B, radio network controller
(RNC), and remote access concentrator (RAC)
applications.
IC provides an integrated octal framer that sup-
ports T1/E1/J1formats.
Supports inverse multiplexing for ATM (IMA) over
selected group and link mappings ranging from
four two-link groups up to one eight-link group per
ATM Forum AF-PHY-0086.001.
Integrates an ATM adaptation layer 2 (AAL2) seg-
mentation and reassembly (SAR) function for sup-
port of low-speed data or voice traffic per ITU
I.363.2.
Provides AAL5 SAR functionality per ITU I.363.5.
Provides quality of service (QoS) connection iden-
tifier (CID) multiplexing per ITU I.366.1.
Enables ATM layer user network interface (UNI) or
IMA mode, selectable on a per-link basis for flexi-
ble transport of delay critical voice and data traffic.
Guarantees QoS for a variety of traffic types
(including delay-sensitive voice, real-time data,
non-real-time data, and signaling information)
through an advanced hierarchical three-level prior-
ity scheduler and per-VC queueing.
Supports 512 bidirectional AAL2 CIDs.
Supports 2032 bidirectional high-speed data con-
nections or virtual circuits (VCs) via embedded
context memory; filters control cells and accepts
control cells via a host microprocessor interface.
On-board memory is used for connection manage-
ment and queue data storage. No external memory
is needed.
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Software package includes the following:
— Device manager source code (C-based device
manager ready-to-use with host RTOS).
— Setup file utility to provision
TAAD08JU21BCLUL3A.
— Firmware for embedded controller (executable
binary).
— API reference manual available for device man-
ager software.
Designed in 0.16 µm, low-power CMOS
technology.
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2 Physical
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3.3 V digital I/O compatibility; 1.5 V core power
520 enhanced ball-grid array (EBGA) package
–40
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C to +85
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C temperature range
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3 Standards
ITU I.363.2, ITU I.363.5, ITU I.366.1, ITU I.366.2,
ITU I.432, ITU I.361, ITU I.371, ITU G.703, ITU
G.704, ITU G.804, ITU G.732, ITU G.706, ITU I.610,
ITU G.775, ITU G.733, ITU G.735, ITU G.965,
ITU O.162,
ANSI
®
T1.403,
ANSI
T1.231,
ATM Forum AF-PHY-0086.001
ATM Forum AF-PHY-0039.000
ATM Forum AF-TM-0121.000
ETS 300.417-1-1
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TAAD08JU21BCLUL3A
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
Table of Contents
Contents
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2
3
4
5
6
7
8
9
Data Sheet, Rev. 1
November 25, 2003
Page
10
11
12
13
Features ............................................................................................................................................................. 1
Physical .............................................................................................................................................................. 1
Standards ........................................................................................................................................................... 1
Description .......................................................................................................................................................12
Pin Definitions ..................................................................................................................................................13
Pin Description .................................................................................................................................................13
Package Pin Layout .........................................................................................................................................22
Block Diagram ..................................................................................................................................................28
Software Components ......................................................................................................................................29
9.1 Firmware.................................................................................................................................................30
9.2 Device Manager......................................................................................................................................30
9.3 Setup File Utility (SFU) ...........................................................................................................................31
9.4 TAAD08JU21BCLUL3A Application Code..............................................................................................32
9.5 System Software.....................................................................................................................................33
9.6 Software Development Environment ......................................................................................................33
9.7 Notes ......................................................................................................................................................34
Functional Overview.........................................................................................................................................35
10.1 Receive Direction Data Flow ..................................................................................................................35
10.1.1 PHY Layer ................................................................................................................................35
10.1.2 Low-Speed PHY Links ..............................................................................................................35
10.1.3 High-Speed PHY Links .............................................................................................................36
10.1.4 TC and IMA Layers...................................................................................................................36
10.1.5 ATM Layer ................................................................................................................................37
10.1.6 AAL Engine...............................................................................................................................37
10.1.7 Embedded Device Controller....................................................................................................38
10.2 Transmit Direction Data Flow..................................................................................................................38
10.2.1 SSCS/AAL Layer Interaction ....................................................................................................38
10.2.2 ATM Layer ................................................................................................................................38
10.2.3 IMA/TC Layer............................................................................................................................39
10.2.4 PHY Layer ................................................................................................................................39
Modes of Operation..........................................................................................................................................40
11.1 Interface Modes ......................................................................................................................................40
11.1.1 UTOPIA-2 Expansion Port Multiplexing Modes ........................................................................40
11.1.2 System Interface Port Multiplexing Modes ...............................................................................40
11.1.3 Line-Interface Modes ................................................................................................................41
11.2 Device Operating Modes ........................................................................................................................41
11.2.1 Operating Mode 1: Internal PHY Mode.....................................................................................41
11.2.2 Operating Mode 2: External PHY Mode ...................................................................................43
11.2.3 Operating Mode 3: SAR-Only Mode .........................................................................................44
11.2.4 Operating Mode Summary........................................................................................................44
Applications ......................................................................................................................................................45
12.1 BTS Network Interface Termination ........................................................................................................45
12.2 VToA Trunking Application......................................................................................................................47
12.3 Low-Speed ATM Access.........................................................................................................................48
12.4 AAL2 Cross Connect ..............................................................................................................................48
Embedded Device Controller (EDC) ................................................................................................................49
13.1 Introduction .............................................................................................................................................49
13.2 Features..................................................................................................................................................49
13.3 EDC Functional Description....................................................................................................................49
13.4 Host Interface .........................................................................................................................................49
13.5 Host Interface Signals and Timing ..........................................................................................................50
Agere Systems Inc.
2
Data Sheet, Rev. 1
November 25, 2003
TAAD08JU21BCLUL3A
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
Table of Contents
(continued)
Contents
Page
13.6 Host Interactions.....................................................................................................................................50
14 Framer Block ....................................................................................................................................................54
14.1 Introduction .............................................................................................................................................54
14.2 Features..................................................................................................................................................54
14.3 Framer-to-Line Interface Unit Physical Interface ....................................................................................55
14.3.1 Line Interface References/Standards .......................................................................................55
14.3.2 Clocking Modes ........................................................................................................................55
14.3.3 Frame Formats .........................................................................................................................56
14.3.4 Transmit Framer Functions.......................................................................................................56
14.4 DS1 Transparent Framing Format ..........................................................................................................56
14.5 CEPT 2.048 Basic Frame Structure Transparent Framing Format.........................................................57
14.6 Receive Framer Nonalignment Mode (DS1/E1) .....................................................................................58
14.6.1 Loss of Frame Alignment Criteria .............................................................................................58
14.6.1.1 Frame Bit Errors .........................................................................................................58
14.6.1.2 CRC Errors.................................................................................................................58
14.7 Frame Alignment Criteria........................................................................................................................58
14.8 Performance-Monitoring Functional Integration Into Framer ..................................................................59
14.9 Performance Report Message................................................................................................................62
14.10 ESF Data Link.........................................................................................................................................63
14.11 Facility Data Link ....................................................................................................................................63
14.11.1 Facility Data Link References/Standards ..................................................................................63
14.11.2 Receive Data Link Functional Description ................................................................................64
14.11.3
SLC-96
Superframe Receive Data Link....................................................................................64
14.11.4 DDS Receive Data Link Stack ..................................................................................................64
14.11.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack .....64
14.11.6 Receive Data Link Stack Idle Modes ........................................................................................65
14.11.7 Transmit Facility Data Link Functional Description ...................................................................65
14.11.8
SLC-96
Superframe Transmit Data Link...................................................................................65
14.11.9 DDS Transmit Data Link Stack .................................................................................................65
14.11.10 Transmit ESF Data Link Bit-Oriented Messages ......................................................................65
14.11.11 CEPT, CEPT Multiframe Transmit Data Link Sa Bits Stack ......................................................66
14.11.12 Transmit Data Link Stack Idle Modes .......................................................................................67
14.11.13
SLC-96,
DDS, or CEPT ESF Frame Alignment ........................................................................67
14.12 Concentration Highway Interface (CHI) ..................................................................................................67
14.12.1 CHI References/Standards .......................................................................................................67
14.12.2 Transmit/Receive CHI Features................................................................................................67
14.12.3 Double NOTFAS System Time-Slot Mode................................................................................68
14.12.4 Transparent Mode.....................................................................................................................68
14.12.5 Loopbacks ................................................................................................................................68
14.12.6 Nominal CHI Timing..................................................................................................................69
14.12.7 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled ................................70
14.12.8 Clocking Scheme......................................................................................................................70
15 Transmission Convergence (TC) Block ............................................................................................................71
15.1 Introduction .............................................................................................................................................71
15.2 Features..................................................................................................................................................71
15.3 TC—Receive Direction ...........................................................................................................................72
15.4 TC—Transmit Direction ..........................................................................................................................72
15.4.1 HEC Generation/Checking .......................................................................................................73
15.5 Cell Delineation.......................................................................................................................................73
15.6 Cell Payload Scrambling/Descrambling..................................................................................................73
15.7 Cell Mapping...........................................................................................................................................73
15.8 Facility Maintenance ...............................................................................................................................73
Agere Systems Inc.
Lucent Technologies—Proprietary
Use pursuant to Company instructions
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TAAD08JU21BCLUL3A
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
Data Sheet, Rev. 1
November 25, 2003
Table of Contents
(continued)
Contents
Page
15.9 Cell Rate Decoupling ..............................................................................................................................74
15.10 Functionality............................................................................................................................................74
16 Inverse Multiplexing for ATM (IMA) Block.........................................................................................................75
16.1 Introduction .............................................................................................................................................75
16.2 Features..................................................................................................................................................76
16.3 Multi-PHY UTOPIA Slave Interface ........................................................................................................77
16.4 Link Processor ........................................................................................................................................77
16.5 Group Processor.....................................................................................................................................78
16.6 Delay Compensation Buffer (DCB).........................................................................................................79
16.7 Programming the DCB............................................................................................................................86
16.7.1 Link Start-Up Guardband Field .................................................................................................86
16.7.2 Link Maximum Operational Delay.............................................................................................86
16.8 Features Not Supported in IMA ..............................................................................................................86
17 ATM Port Controller (APC) Block .....................................................................................................................88
17.1 Introduction .............................................................................................................................................88
17.2 Architecture.............................................................................................................................................89
17.3 Features..................................................................................................................................................90
17.4 Summary of Commands .........................................................................................................................91
17.5 Buffer Management ................................................................................................................................91
17.6 Scheduling ..............................................................................................................................................93
17.6.1 Ingress Scheduling ...................................................................................................................93
17.6.2 Fabric Backpressure.................................................................................................................94
17.6.3 Egress Scheduling....................................................................................................................94
17.7 ABR Flow Control ...................................................................................................................................94
17.8 Control Plane Functions .........................................................................................................................95
17.8.1 APC Support for Control Plane Functions ................................................................................95
17.9 Management Plane Functions ................................................................................................................95
17.9.1 Operation Administration and Maintenance (OAM) ..................................................................95
17.10 Statistics Counters ..................................................................................................................................96
17.11 Ingress Enqueue Operations ..................................................................................................................96
17.11.1 Connection Look-Up .................................................................................................................97
17.11.2 OAM Processing.......................................................................................................................98
17.11.3 Policing .....................................................................................................................................99
17.11.4 Buffer Thresholding ..................................................................................................................99
17.11.5 Egress—APC VC Queueing Structure......................................................................................99
17.12 Connection Management......................................................................................................................100
17.12.1 Connection Admission Control ...............................................................................................100
17.12.1.1 CBR..........................................................................................................................100
17.12.1.2 rt-VBR ......................................................................................................................100
17.12.1.3 nrt-VBR ....................................................................................................................100
17.12.1.4 ABR..........................................................................................................................100
17.12.1.5 UBR..........................................................................................................................100
18 ATM Adaptation Layer (AAL) Block ................................................................................................................101
18.1 Introduction ...........................................................................................................................................101
18.2 Features................................................................................................................................................101
18.3 Definitions .............................................................................................................................................102
18.4 Architecture...........................................................................................................................................103
18.4.1 Datapath Flows .......................................................................................................................103
18.4.2 Subblock Architecture.............................................................................................................106
18.4.3 Subblock Definition .................................................................................................................107
18.4.4 Subblock Flows.......................................................................................................................108
18.4.5 Address Translation ................................................................................................................109
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Lucent Technologies—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
Data Sheet, Rev. 1
November 25, 2003
TAAD08JU21BCLUL3A
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
Table of Contents
(continued)
Contents
18.4.6
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.4.16
18.4.17
18.4.18
Page
Queueing and Scheduling ...................................................................................................... 110
Modes ..................................................................................................................................... 110
User Data Types (UDT) and AAL Types ................................................................................. 111
UDT: ATM Cell ........................................................................................................................ 112
AAL Type: AAL0 ..................................................................................................................... 112
AAL Type: AAL2 ..................................................................................................................... 112
AAL2 Subtype: SPAAL2 (Single-Packet AAL2) ...................................................................... 113
CPS-AAL0 .............................................................................................................................. 114
AAL Type: AAL5 ..................................................................................................................... 114
UDT: Packet ATM (PATM)....................................................................................................... 115
UDT: HPF................................................................................................................................ 116
AAL Type: NPAAL (No Particular AAL)................................................................................... 117
Nonuser Data Types: ESI Messages ...................................................................................... 117
18.4.18.1 ESI Message Format ............................................................................................... 117
18.4.18.2 ESI Violation Code ................................................................................................... 118
18.4.18.3 ESI Packet Length ................................................................................................... 118
18.4.19 Service Types ......................................................................................................................... 118
18.4.20 CPS_SERVICE....................................................................................................................... 119
18.4.21 SEG_AAL2_SSSAR_SERVICE .............................................................................................120
18.4.22 SEG_AAL2_SSTED_SERVICE..............................................................................................120
18.4.23 SEG_AAL5_SERVICE............................................................................................................120
18.4.24 TRANSPARENT_SERVICE....................................................................................................121
18.4.25 REASS_AAL2_SSSAR_SERVICE .........................................................................................121
18.4.26 REASS_AAL2_SSTED_SERVICE .........................................................................................121
18.4.27 REASS_AAL5_SERVICE .......................................................................................................121
18.5 Provisioning ..........................................................................................................................................123
18.5.1 Some Notes on Terminology and Command Referencing......................................................123
18.5.2 System Interface.....................................................................................................................123
18.5.3 Port Table................................................................................................................................124
18.5.4 MEMI Shared Memory............................................................................................................125
18.5.4.1 MEMI-SM Provisioning Constraints..........................................................................126
18.5.4.2 VC Table...................................................................................................................126
18.5.4.3 AAL2 VC Table .........................................................................................................127
18.5.4.4 Connection Table .....................................................................................................128
18.5.4.5 Level 0 Queue Descriptor ........................................................................................130
18.5.4.6 ICID Table ................................................................................................................130
18.5.5 SQASE Shared Memory .........................................................................................................130
18.6 Configuration ........................................................................................................................................131
18.6.1 Connection and Channel Setup..............................................................................................131
18.6.1.1 AAL2 Data Flow (CPS/SSSAR/SSTED) ..................................................................134
18.6.1.2 CPS-AAL0 Data Flow...............................................................................................134
18.6.1.3 AAL0/AAL5 Data Flow..............................................................................................134
18.6.1.4 HPF Data Flow .........................................................................................................134
18.6.2 Configuration for QoS .............................................................................................................135
18.6.2.1 Packet Scheduling ...................................................................................................135
18.6.2.2 IL1Q Scheduler Algorithm ........................................................................................135
18.6.2.3 IL2Q Scheduler Algorithm ........................................................................................135
18.6.2.4 Latency Policing .......................................................................................................137
18.6.2.5 Latency-Sensitive Data Discard ...............................................................................137
18.6.2.6 Internal Queue Housekeeping .................................................................................137
18.6.2.7 Reference Clock Generation ....................................................................................137
18.6.2.8 Latency Timer Enable/Disable Functions.................................................................138
Agere Systems Inc.
Lucent Technologies—Proprietary
Use pursuant to Company instructions
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