The information contained herein is subject to change without notice. 021023_D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the
“Handling
Guide for
Semiconductor Devices,” or
“TOSHIBA
Semiconductor Reliability Handbook” etc. 021023_A
The TOSHIBA products listed in this document are designed and manufactured for usage in
Automotive applications. These TOSHIBA products are neither intended nor warranted for usage in
equipment other than Automotive applications that requires extraordinarily high quality and/or
reliability or a malfunction or failure of which may cause loss of human life or bodily injury
(“Unintended Usage”). Unintended Usage includes atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. TOSHIBA product listed in this
document shall not be used for other than Automotive applications such as the applications listed
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The products described in this document shall not be used or embedded to any downstream products of
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060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patents or other rights of TOSHIBA or the third parties. 070122_C
The products described in this document are subject to foreign exchange and foreign trade control
laws. 060925_E
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2007 TOSHIBA CORPORATION
All Rights Reserved
Table of Contents
TMP88CH40IMG
1.1
1.2
1.3
1.4
Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Names and Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
4
5
2.
Functional Description
2.1
Functions of the CPU Core
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Address Map...............................................................................................................................
Program Memory (ROM)
..........................................................................................................................
Data Memory (RAM)
.................................................................................................................................
System Clock Control Circuit
....................................................................................................................
Clock Generator
Timing Generator
Standby Control Circuit
Controlling Operation Modes
External Reset Input
Adress Trap Reset
Watchdog Timer Reset
System Clock Reset
2.1.1
2.1.2
2.1.3
2.1.4
7
8
8
9
2.1.5
2.1.4.1
2.1.4.2
2.1.4.3
2.1.4.4
2.1.5.1
2.1.5.2
2.1.5.3
2.1.5.4
Reset Circuit
........................................................................................................................................... 17
3.
Interrupt Control Circuit
3.1
3.2
3.3
Interrupt latches (IL38 to IL2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt enable register (EIR)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt Sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interrupt acceptance processing is packaged as follows........................................................................
24
Saving/restoring general-purpose registers
............................................................................................ 25
Using Automatic register bank switcing
Using register bank switching
Using PUSH and POP instructions
Using data transfer instructions
3.2.1
3.2.2
Interrupt master enable flag (IMF)
.......................................................................................................... 21
Individual interrupt enable flags (EF38 to EF3)
...................................................................................... 21
3.3.1
3.3.2
3.4
3.5
3.3.3
3.4.1
3.4.2
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
Software Interrupt (INTSW)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Address error detection
.......................................................................................................................... 28
Debugging
.............................................................................................................................................. 28
Interrupt return
........................................................................................................................................ 27
4.
Special Function Register
4.1
4.2
SFR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DBR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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