PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4584 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0010-0300Z
Rev.3.00
2004.08.06
DESCRIPTION
The 4584 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
four 8-bit timers (each timer has one or two reload registers), a 10-
bit A/D converter, interrupts, and oscillation circuit switch function.
The various microcomputers in the 4584 Group include variations
of the built-in memory type as shown in the table below.
FEATURES
qMinimum
instruction execution time .................................. 0.5
µ
s
(at 6 MHz oscillation frequency, in X
IN
through-mode)
qSupply
voltage
Mask ROM version ...................................................... 1.8 to 5.5 V
One Time PROM version ............................................. 2.5 to 5.5 V
(It depends on operation source clock, oscillation frequency and op-
eration mode)
qTimers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
Timer 3 ...................................... 8-bit timer with a reload register
Timer 3 ................................. 8-bit timer with two reload registers
qInterrupt
........................................................................ 7 sources
qKey-on
wakeup function pins ................................................... 10
q
A/D converter .......... 10-bit successive comparison method, 2ch
qVoltage
drop detection circuit
Reset occurrence .................................... Typ. 1.5 V (Ta = 25 °C)
Reset release .......................................... Typ. 1.6 V (Ta = 25 °C)
qWatchdog
timer
qClock
generating circuit
(ceramic resonator/RC oscillation/quartz-crystal oscillation/on-
chip oscillator)
qLED
drive directly enabled (port D)
APPLICATION
Remote control transmitter
Part number
M34584MD-XXXFP
M34584EDFP (Note)
Note:
Shipped in blank.
ROM (PROM) size
(✕ 10 bits)
16384 words
16384 words
RAM size
(✕ 4 bits)
384 words
384 words
Package
42P2R-A
42P2R-A
ROM type
Mask ROM
One Time PROM
Rev.3.00 2004.08.06
REJ03B0010-0300Z
page 1 of 155
PRELIMINARY
4584 Group
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION
P1
3
D
0
D
1
D
2
D
3
D
4
D
5
D
6
/CNTR
0
C/CNTR
1
P5
0
P5
1
P5
2
P5
3
P2
0
P2
1
P2
2
RESET
CNV
SS
X
OUT
X
IN
V
SS
1
2
3
4
5
6
42
41
40
39
38
37
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P1
2
P1
1
P1
0
P0
3
P0
2
P0
1
P0
0
P4
3
P4
2
P4
1
P4
0
P6
3
P6
2
P6
1
/A
IN1
P6
0
/A
IN0
P3
3
P3
2
P3
1
/INT1
P3
0
/INT0
VDCE
V
DD
OUTLINE 42P2R-A
M34584MD-XXXFP
M34584EDFP
Pin configuration (top view) (4584 Group)
Rev.3.00 2004.08.06
REJ03B0010-0300Z
page 2 of 155
4584 Group
Block diagram (4584 Group)
Rev.3.00 2004.08.06
REJ03B0010-0300Z
4
4
3
4
4
4
4
I/O port
Port P1
Port P3
Port P4
Port P5
Port P6
Port P2
System clock generation circuit
X
IN
-X
OUT
(Ceramic/Quartz-crystal/RC)
On-chip oscillator
Port P0
Internal peripheral functions
page 3 of 155
Timer
Timer 1(8 bits)
Timer 2(8 bits)
Timer 3(8 bits)
Timer 4(8 bits)
Voltage drop detection circuit
Watchdog timer (16 bits)
A/D converter
(10 bits
✕
2 ch)
Memory
ROM
16384 words
✕
10 bits
4500 series
CPU core
ALU(4 bits)
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
RAM
384 words
✕
4 bits
Port C
1
Port D
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PRELIMINARY
4584 Group
Notice: This is not a final specification.
Some parametric limits are subject to change.
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes ROM
RAM
I/O (Input is
Input/Output D
0
–D
6
examined by
ports
skip decision)
P0
0
–P0
3
I/O
P1
0
–P1
3
I/O
P2
0
–P2
2
P3
0
–P3
3
P4
0
–P4
3
P5
0
–P5
3
P6
0
–P6
3
Timer 1
Timer 2
Timer 3
Timer 4
A/D converter
Sources
Interrupt
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage Mask ROM version
One Time PROM version
Active mode
Power
dissipation
(typical value)
RAM back-up mode
I/O
I/O
I/O
I/O
I/O
154
0.5
µ
s (at 6.0 MHz oscillation frequency, in X
IN
through-mode)
16384 words
✕
10 bits
384 words
✕
4 bits
Seven independent I/O ports;
Port D
6
is also used as CNTR0, respectively.
The output structure is switched by software.
4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched
by software.
3-bit I/O port
4-bit I/O port ; ports P3
0
and P3
1
are also used as INT0 and INT1, respectively.
4-bit I/O port
4-bit I/O port ; the output structure is switched by software.
4-bit I/O port ; ports P6
0
, P6
1
are also used as A
IN0
, A
IN1
, respectively.
8-bit timer with a reload register is also used as an event counter.
Also, this is equipped with a period/pulse width measurement function.
8-bit timer with a reload register.
8-bit timer with a reload register is also used as an event counter.
8-bit timer with two reload registers and PWM output function.
10-bit wide
✕
2 ch, This is equipped with an 8-bit comparator function.
7 (two for external, four for timer, one for A/D)
1 level
8 levels
CMOS silicon gate
42-pin plastic molded SSOP (42P2R-A)
–20 °C to 85 °C
1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.5 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.8 mA (Ta=25°C, V
DD
=5V, f(X
IN
)=6 MHz, f(STCK)=f(X
IN
), on-chip oscillator stop)
70
µA
(Ta=25°C, V
DD
=5V, f(X
IN
)=32 kHz, f(STCK)=f(X
IN
), on-chip oscillator stop)
150
µA
(Ta=25°C, V
DD
=5V, on-chip oscillator is used, f(STCK)=f(RING), f(X
IN
) stop)
0.1
µ
A (Ta=25°C, V
DD
= 5 V, output transistors in the cut-off state)
Function
Timers
Rev.3.00 2004.08.06
REJ03B0010-0300Z
page 4 of 155
PRELIMINARY
4584 Group
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Pin
V
DD
V
SS
CNV
SS
VDCE
Name
Power supply
Ground
CNV
SS
Voltage drop
detection circuit
enable
Reset input/output
Function
Input/Output
Connected to a plus power supply.
—
Connected to a 0 V power supply.
—
Connect CNV
SS
to V
SS
and apply “L” (0V) to CNV
SS
certainly.
—
Input
This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is
input to this pin, the circuit starts operating. When “L“ level is input to this pin, the
circuit stops operating.
An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the built-in power-on reset or the voltage drop detection circuit
causes the system to be reset, the
RESET
pin outputs “L” level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect
it between pins X
IN
and X
OUT
. When using a 32 kHz quartz-crystal oscillator, connect it
between pins X
IN
and X
OUT
. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to X
IN
, and leave X
OUT
pin open.
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Port D
6
is
also used as CNTR0 pin.
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P2 serves as a 3-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P3
0
and P3
1
are also used as INT0 pin and INT1 pin, respectively.
Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain. For input use, set the latch of the specified bit to “1”.
Port P5 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain.
Port P6 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain. For input use, set the latch of the specified bit to “1”. Ports P6
0
, P6
1
are
also used as A
IN0
, A
IN1
, respectively.
Port C serves as a 1-bit port. The output structure is CMOS. For input use, set the
latch of the specified bit to “1”. Port C is also used as CNTR1.
CNTR0 pin has the function to input the clock for the timer 1 event counter, and to
output the timer 1 or timer 2 underflow signal divided by 2.
CNTR1 pin has the function to input the clock for the timer 3 event counter, and to
output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also
used as Ports D
6
and C, respectively.
INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup func-
tion which can be switched by software. INT0 pin and INT1 pin are also used as
Ports P3
0
and P3
1
, respectively.
A/D converter analog input pins. A
IN0
pin and A
IN1
pin are also used as Ports P6
0
and
P6
1
, respectively.
RESET
I/O
X
IN
X
OUT
D
0
–D
6
Main clock input
Main clock output
I/O port D
Input is examined by
skip decision.
I/O port P0
Input
Output
I/O
P0
0
–P0
3
I/O
P1
0
–P1
3
I/O port P1
I/O
P2
0
–P2
3
P3
0
–P3
3
I/O port P2
I/O port P3
I/O
I/O
P4
0
–P4
3
P5
0
–P5
3
I/O port P4
I/O port P5
I/O
I/O
P6
0
–P6
3
I/O port P6
I/O
C
CNTR0,
CNTR1
Output port C
Timer input/output
Output
I/O
INT0, INT1
Interrupt input
Input
A
IN0
, A
IN1
Analog input
Input
Rev.3.00 2004.08.06
REJ03B0010-0300Z
page 5 of 155
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