4508 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0148-0102
Rev.1.02
2006.12.22
DESCRIPTION
The 4508 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a simple,
high-speed instruction set. The computer is equipped with two 8-bit
timers (each timer has two reload registers), interrupts, 10-bit A/D
converter, Serial interface and oscillation circuit switch function.
FEATURES
qMinimum
instruction execution time .................................. 0.5
µ
s
(at 6 MHz oscillation frequency, in through-mode)
qSupply
voltage .......................................................... 1.8 V to 5.5 V
(It depends on operation source clock, oscillation frequency and
operating mode.)
qTimers
Timer 1 ................................. 8-bit timer with two reload registers
Timer 2 ................................. 8-bit timer with two reload registers
qInterrupt
........................................................................ 5 sources
ROM (PROM) size
(✕ 10 bits)
4096 words
4096 words
4096 words
4096 words
4096 words
4096 words
4096 words
4096 words
*: Under development
qKey-on
wakeup function pins ................................................... 12
qInput/Output
port ...................................................................... 14
qA/D
converter
10-bit successive comparison method ........................ 4 channel
qSerial
intereface ............................................................. 8-bit
✕
1
qVoltage
drop detection circuit (only for H version)
Reset occurrence .................................... Typ. 2.6 V (Ta = 25 °C)
Reset release .......................................... Typ. 2.7 V (Ta = 25 °C)
qPower-on
reset circuit (only for H version)
qWatchdog
timer
qClock
generating circuit (on-chip oscillator/ceramic resonator/RC
oscillation)
qLED
drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office
automation equipment, etc.
RAM size
(✕ 4 bits)
256 words
256 words
256 words
256 words
256 words
256 words
256 words
256 words
Part number
M34508G4FP (Note)
M34508G4-XXXFP
M34508G4HFP (Note)
M34508G4H-XXXFP
M34508G4GP * (Note)
M34508G4-XXXGP *
M34508G4HGP * (Note)
M34508G4H-XXXGP *
Note:
Shipped in blank.
Package
PRSP0020DA-A
PRSP0020DA-A
PRSP0020DA-A
PRSP0020DA-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
ROM type
QzROM
QzROM
QzROM
QzROM
QzROM
QzROM
QzROM
QzROM
PIN CONFIGURATION
V
DD
V
SS
X
IN
X
OUT
CNV
SS
RESET
P2
1
/A
IN1
P2
0
/A
IN0
D
3
/A
IN5
D
2
/A
IN4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P0
0
/S
IN
P0
1
/S
OUT
P0
2
/S
CK
P0
3
P1
0
P1
1
/CNTR1
P1
2
/CNTR0
P1
3
/INT
D
0
D
1
Outline FP: PRSP0020DA-A (20P2N-A)
GP: PLSP0020JB-A (20P2F-A)
Pin configuration (top view) (4508 Group)
M34508G4-XXXFP/GP
M34508G4FP/GP
M34508G4H-XXXFP/GP
M34508G4HFP/GP
Rev.1.02 2006.12.22
REJ03B0148-0102
page 1 of 140
4508 Group
Rev.1.02 2006.12.22
REJ03B0148-0102
4
4
2
4
Port P0
Port P1
Port P2
Port D
Timer
System clock generating circuit
X
IN
-X
OUT
(Ceramic/RC)
On-chip oscillator
Power-on reset circuit (Note)
Voltage drop detection circuit (Note)
Block diagram (4508 Group)
I/O port
page 2 of 140
Internal peripheral functions
Timer 1 (8 bits)
Timer 2 (8 bits)
Watchdog timer
(16 bits)
Memory
ROM
4096 words
✕
10 bits
A/D converter
(10 bits
✕
4 ch)
4500 Series
CPU core
ALU (4 bits)
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1level)
Serial interface
(8 bits
✕
1)
RAM
256 words
✕
4 bits
Note: The voltage drop detection circuit is equipped with only H version.
4508 Group
PERFORMANCE OVERVIEW
Parameter
Number of
basic instructions
M34508G4
M34508G4H
Minimum instruction execution time
Memory sizes ROM
Input/Output
ports
RAM
D
0
–D
3
I/O
131
132
0.5
µ
s (at 6 MHz oscillation frequency, in through mode)
4096 words
✕
10 bits
256 words
✕
4 bits
Four independent I/O ports.
Input is examined by skip decision.
Ports D
2
and D
3
are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D
2
and D
3
are also used as A
IN4
, and A
IN5
, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P0
0
, P0
1
and P0
2
are also used as S
IN
, S
OUT
and S
CK
, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P1
1
, P1
2
and P1
3
are also used as CNTR1, CNTR0 and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
Two independent I/O; CNTR1 and CNTR0 pins are also used as ports P1
1
and P1
2
, respectively.
1-bit input; INT pin is also used as port P1
3
.
Three independent I/O;
S
IN
, S
OUT
, and S
CK
are also used as ports P0
0
, P0
1
, and P0
2
, respectively.
Four independent input; A
IN0
, A
IN1
, A
IN4
, A
IN5
are also used as P2
0
, P2
1
, D
2
and D
3
, respectively.
8-bit programmable timer/event counter with two reload registers and PWM output function.
8-bit programmable timer/event counter with two reload registers and PWM output function.
16-bit timer (fixed dividing frequency) (for watchdog)
10-bit wide, This is equipped with an 8-bit comparator function.
4 channel (A
IN0
, A
IN1
, A
IN4
, A
IN5
pins)
8-bit
✕
1
Typ. 2.6 V (Ta = 25 °C)
Typ. 2.7 V (Ta = 25 °C)
Built-in type
5 (one for external, two for timer, one for A/D, one for Serial interface)
1 level
8 levels
CMOS silicon gate
FP: 20-pin plastic molded SOP (PRSP0020DA-A)
GP: 20-pin plastic molded SSOP (PLSP0020JB-A)
–20 °C to 85 °C
1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.2 mA (Ta = 25°C, V
DD
= 5.0 V, f(X
IN
) = 6.0 MHz, f(STCK) = f(X
IN
)/1)
0.1
µ
A (Ta = 25°C, V
DD
= 5.0 V, output transistors in the cut-off state)
Function
P0
0
–P0
3
I/O
P1
0
–P1
3
I/O
P2
0
, P2
1
I/O
CNTR0,
CNTR1
INT
Timer I/O
Interrupt input
S
IN
, S
OUT
, Serial interface
S
CK
input/output
A
IN0
, A
IN1,
Analog input
A
IN4
, A
IN5
Timers
Timer 1
Timer 2
Watchdog timer function
A/D
converter
Analog input
Serial interface
Voltage drop Reset occurrence
detection
Reset release
circuit (Note)
Power-on reset circuit (Note)
Interrupt
Sources
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
Active mode
dissipation
RAM back-up mode
(typical value)
Note: These circuits are equipped with only the H version.
Rev.1.02 2006.12.22
REJ03B0148-0102
page 3 of 140
4508 Group
PIN DESCRIPTION
Pin
V
DD
V
SS
CNV
SS
RESET
Name
Power supply
Ground
CNV
SS
Reset input/output
Function
Input/Output
Connected to a plus power supply.
—
Connected to a 0 V power supply.
—
Connect CNV
SS
to V
SS
and apply “L” (0V) to CNV
SS
certainly.
—
An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watch-
I/O
dog timer, the voltage drop detection circuit (only for H version) or the built-in power-on
reset (only for H version) causes the system to be reset, the RESET pin outputs “L”
level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it be-
Input
tween pins X
IN
and X
OUT
. A feedback resistor is built-in between them. When using the RC
Output
oscillation, connect a resistor and a capacitor to X
IN
, and leave X
OUT
pin open.
Each pin of port D has an independent 1-bit wide I/O function.
I/O
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Ports D
2
and D
3
are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D
2
and D
3
are also used as A
IN4
and A
IN5
, respectively.
Port P0 serves as a 4-bit I/O port.
I/O
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P0 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P0
0
, P0
1
and P0
2
are also used as S
IN
, S
OUT
and S
CK
, respectively.
Port P1 serves as a 4-bit I/O port.
I/O
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P1 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P1
1
, P1
2
and P1
3
are also used as CNTR1, CNTR0 and INT, respectively.
I/O
Port P2 serves as a 2-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P2 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
CNTR0 pin has the function to input the clock for the timer 2 event counter, and to out-
put the PWM signal generated by timer 1.
This pin is also used as port P1
2
.
CNTR1 pin has the function to input the clock for the timer 1 event counter, and to out-
put the PWM signal generated by timer 2.
This pin is also used as port P1
1
.
INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software.
This pin is also used as port P1
3
.
A/D converter analog input pins.
A
IN0
, A
IN1
, A
IN4
, A
IN5
are also used as ports P2
0
, P2
1
, D
2
and D
3
, respectively.
Serial interface data transfer synchronous clock I/O pin. S
CK
pin is also used as port P0
2
.
Serial interface data output pin. S
OUT
pin is also used as port P0
1
.
Serial interface data input pin. S
IN
pin is also used as port P0
0
.
X
IN
X
OUT
D
0
–D
3
System clock input
System clock output
I/O port D
Input is examined by
skip decision.
P0
0
–P0
3
I/O port P0
P1
0
–P1
3
I/O port P1
P2
0
, P2
1
I/O port P2
CNTR0
Timer input/output
I/O
CNTR1
Timer input/output
I/O
INT
Interrupt input
Input
A
IN0
, A
IN1,
Analog input
A
IN4
, A
IN5,
S
CK
Serial interface clock I/O
S
OUT
Serial interface data output
S
IN
Serial interface data input
Input
I/O
Output
Input
Rev.1.02 2006.12.22
REJ03B0148-0102
page 4 of 140
4508 Group
MULTIFUNCTION
Pin
P0
0
P0
1
P0
2
P1
1
P1
2
P1
3
Multifunction
S
IN
S
OUT
S
CK
CNTR1
CNTR0
INT
Pin
S
IN
S
OUT
S
CK
CNTR1
CNTR0
INT
Multifunction
P0
0
P0
1
P0
2
P1
1
P1
2
P1
3
Pin
P2
0
P2
1
D
2
D
3
Multifunction
A
IN0
A
IN1
A
IN4
A
IN5
Pin
A
IN0
A
IN1
A
IN4
A
IN5
Multifunction
P2
0
P2
1
D
2
D
3
Notes 1: Pins except above have just single function.
2: The input/output of P0
0
can be used even when S
IN
is used. Be careful when using inputs of both S
IN
and P0
0
since the input threshold value of S
IN
pin
is different from that of port P0
0
.
3: The input of P0
1
can be used even when S
OUT
is used.
4: The input of P0
2
can be used even when S
CK
is used. Be careful when using inputs of both S
CK
and P0
2
since the input threshold value of S
CK
pin is
different from that of port P0
2
.
5: The input of P1
1
can be used even when CNTR1 (output) is selected.
The input/output of P1
1
can be used even when CNTR1 (input) is selected. Be careful when using inputs of both CNTR1 and P1
1
since the input thresh-
old value of CNTR1 pin is different from that of port P1
1
.
6: The input of P1
2
can be used even when CNTR0 (output) is selected.
The input/output of P1
2
can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and P1
2
since the input thresh-
old value of CNTR0 pin is different from that of port P1
2
.
7: The input/output of P1
3
can be used even when INT is used. Be careful when using inputs of both INT and P1
3
since the input threshold value of INT
pin is different from that of port P1
3
.
8: The input/output of P2
0
, P2
1
, D
2
, D
3
can be used even when A
IN0
, A
IN1
, A
IN4
, A
IN5
are used.
PORT FUNCTION
Port
Port D
D
0
, D
1
D
2
/A
IN4
D
3
/A
IN5
Pin
Input
Output
I/O
(4)
Output structure
N-channel open-drain/
CMOS
I/O
Control
Control
Remark
unit instructions registers
1
SD, RD
Programmable output structure selection
FR3
SZD, CLD
function
FR3, PU2
K2
Q1
I/O
(4)
N-channel open-drain/
CMOS
4
OP0A
IAP0
FR0, PU0
K0
J1
FR1, PU1
K1, L1, I1
W1, W2
W5, W6
FR2, PU2
Q1
K2
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
Port P0 P0
0
/S
IN
, P0
1
/S
OUT
,
P0
2
/S
CK
, P0
3
Port P1 P1
0
, P1
1
/CNTR1,
P1
2
/CNT0,
P1
3
/INT
Port P2 P2
0
/A
IN0
P2
1
/A
IN1
I/O
(4)
N-channel open-drain/
CMOS
4
OP1A
IAP1
I/O
(2)
N-channel open-drain/
CMOS
2
OP2A
IAP2
Rev.1.02 2006.12.22
REJ03B0148-0102
page 5 of 140
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