DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD431636L
1M-BIT CMOS SYNCHRONOUS FAST SRAM
32K-WORD BY 36-BIT
PIPELINED OPERATION
Description
The
µ
PD431636L is a 32,768-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology
using N-channel four-transistor memory cell.
The
µ
PD431636L integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as
SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
The
µ
PD431636L is suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
•
The
µ
PD431636LGF is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
•
3.3 V (Chip) / 3.3 V or 2.5 V (I/O) Supply
•
Synchronous Operation
•
Internally self-timed Write control
•
Burst Read / Write: Interleaved Burst and Linear Burst Sequence
•
Fully Registered Inputs and Outputs for Pipelined operation
•
All Registers triggered off Positive Clock Edge
•
3.3 V or 2.5 V LVTTL Compatible : All Inputs and Outputs
•
Fast Clock Access Time: 4.6 ns (150 MHz), 5 ns (133 MHz)
•
Asynchronous Output Enable: /G
•
Burst Sequence Selectable: MODE
•
Sleep Mode: ZZ (ZZ = Open or Low : Normal Operation )
•
Separate Byte Write Enable: /BW1 - /BW4, /BWE
Global Write Enable: /GW
•
Three Chip Enables for Easy Depth Expansion
•
Common I/O Using Three State Outputs
•
Ordering Information
Part number
Access Time Clock frequency
4.6 ns
5.0 ns
150 MHz
133 MHz
Package
100-pin plastic LQFP (14x20 mm)
100-pin plastic LQFP (14x20 mm)
µ
PD431636LGF-A6
µ
PD431636LGF-A7
The information in this document is subject to change without notice.
Document No. M12179EJ5V0DS00 (5th edition)
Date Published July 1998 NS CP(K)
Printed in Japan
The mark
•
shows major revised points.
©
1996
µ
PD431636L
Pin Configuration(Marking Side)
/xxx indicates active low signal.
•
100-pin plastic LQFP (14 x 20 mm)
[
µ
PD431636LGF]
/BWE
/BW4
/BW3
/BW2
/BW1
/ADV
/CE2
/GW
CLK
CE2
V
DD
V
SS
/AC
/CE
/AP
A6
A7
A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
DD
V
SS
NC
NC
A10
A11
A12
A13
A14
NC
2
NC
A9
/G
µ
PD431636L
Pin Identification
Symbol
A0 - A14
I/O1 - I/O32
Pin No.
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48 Synchronous Address Input
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, Synchronous Data In,
79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 Synchronous / Asynchronous Data Out
1, 30, 51, 80
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
/OP1 - I/OP4
/ADV
/AP
/AC
/CE, CE2, /CE2
83
84
85
98, 97, 92
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
Asynchronous Burst Sequence Select Input
Have to be tied to V
DD
or V
SS
during normal
operation
/BW1 - /BW4, /BWE 93, 94, 95, 96, 87
/GW
/G
CLK
MODE
88
86
89
31
ZZ
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
64
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
14, 16, 38, 39, 42, 43, 49, 50, 66
Asynchronous Power Down State Input
Power Supply
Ground
Output Buffer Power Supply
Output Buffer Ground
No Connection
3
µ
PD431636L
Block Diagram
A0 - A14
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
4
I/O1 - I/O32
I/OP1 - I/OP4
ZZ
36
Power down control
Enable
register
Enable delay
register
Input
register
15
Address
register
15
A0, A1
13
15
Binary Q1
A1’
counter
and logic
CLR
Q0
A0’
Byte 1
Write register
Byte 2
Write register
Byte 3
Write register
Byte 4
Write register
9
9
9
9
Byte 1
Write driver
Byte 2
Write driver
Byte 3
Write driver
Byte 4
Write driver
36
Row & column
decoder
Memory matrix
512 rows
64
×
36 columns
(1,179,648 bits)
36
Output
register
Output
buffer
Burst Sequence
Interleaved Burst Sequence Table (MODE = Open or V
DD
)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A14 - A2, A1, A0
A14 - A2, A1, /A0
A14 - A2, /A1, A0
A14 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A14 - A2, 0, 0
A14 - A2, 0, 1
A14 - A2, 1, 0
A14 - A2, 1, 1
A14 - A2, 0, 1
A14 - A2, 1, 0
A14 - A2, 1, 1
A14 - A2, 0, 0
A14 - A2, 1, 0
A14 - A2, 1, 1
A14 - A2, 0, 0
A14 - A2, 0, 1
A14 - A2, 1, 1
A14 - A2, 0, 0
A14 - A2, 0, 1
A14 - A2, 1, 0
4
µ
PD431636L
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
/G
L
H
X
X
I/O
Dout
Hi-Z
Hi-Z, Din
Hi-Z
Remark
X means “don’t care.”
Synchronous Truth Table
Operation
Deselected
Deselected
Deselected
Deselected
Deselected
Note
Note
Note
Note
Note
/CE
H
L
L
L
L
L
L
X
H
X
H
L
X
H
X
H
CE2
X
L
X
L
X
H
H
X
X
X
X
H
X
X
X
X
/CE2
X
X
H
X
H
L
L
X
X
X
X
L
X
X
X
X
/AP
X
L
L
H
H
L
H
H
X
H
X
H
H
X
H
X
/AC
L
X
X
L
L
X
L
H
H
H
H
L
H
H
H
H
/ADV
X
X
X
X
X
X
X
L
L
H
H
X
L
L
H
H
/WRITE
X
X
X
X
X
X
H
H
H
H
H
L
L
L
L
L
CLK
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
Address
N/A
N/A
N/A
N/A
N/A
External
External
Next
Next
Current
Current
External
Next
Next
Current
Current
Read Cycle / Begin Burst
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Suspend Burst
Read Cycle / Suspend Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Suspend Burst
Write Cycle / Suspend Burst
Note
Deselect status is held until new “Begin Burst” entry.
Remarks 1.
X means “don’t care.”
2.
/WRITE=L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE=H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW.
5
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