RD15LD74AP, RD15LD74ANP, RD15LD74AT
8-bit D-type Flip-Flop Driver (with Clear)
REJ03D0894-0300
Rev.3.00
Feb 29, 2008
Description
RD15LD74AP, RD15LD74ANP, RD15LD74AT have eight D-type flip-flop drivers and high voltage NMOS output
(open drain output) in a 20 pin package. Each bit, there are a common clear and clock input. The input signal is output
with the rising edge of clock signals. The voltage of maximum 15 V can be impressed to the drain-source voltage.
Features
•
•
•
•
•
•
•
•
Application of amusement equipment.
Output voltage : V
DS
(max) = 15 V
Output current : I
DS
(max) = 200 mA (par pin)
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –20 to +85 °C
Quiescent supply current : 5 µA max.
Low input current : 1 µA max.
Ordering Information
Part Name
RD15LD74APT0
RD15LD74ANPT0
RD15LD74ATH0
Note:
Package Type
SDIP-20 pin
DILP-20 pin
TSSOP-20 pin
Package Code
(Previous Code)
PRDP0020BA-A
(20P4B)
PRDP0020AC-B
(DP-20NEV)
PTSP0020JB-A
(TTP-20DAV)
Package
Abbreviation
P
P
T
Packing Abbreviation
(Quantity)
T (1,125 pcs/box)
T (1,000 pcs/box)
H (2,000 pcs/reel)
Surface
Treatment
0 (Sn-Cu)
0 (Ni/Pd/Au)
0 (Ni/Pd/Au)
Please consult the sales office for the above package availability.
Pin Arrangement
CLR
1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
CLK 10
(Top view)
20 V
CC
19
Y0
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11 GND
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 1 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Logic Diagram
Y
0
19
Y
1
18
Y
2
17
Y
3
16
Y
4
15
Y
5
14
Y
6
13
Y
7
12
V
CC
20
10
CLK
D
CK
R
CLR
1
2
D
0
D
1
3
D
2
4
D
3
5
D
4
6
D
5
7
D
6
8
D
7
9
11
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
GND
Note: Schmitt trigger circuit is added to all input. V
H
= 1.5 V (TYP)
Function Table
CLR
L
H
H
H
H
Inputs
CLK
X
↑
↑
L
↓
D
X
L
H
X
X
Output
Y
Z
Z
L
Y
0
Y
0
H : High level
L : Low level
X : Immaterial
Z : High Impedance
↑
: Low to High transition
↓
: High to Low transition
Y
0
: Level of
Y
before the indicated steady input conditions were established.
Timing Figure
V
CC
CLK
GND
V
CC
D
GND
V
CC
CLR
GND
V
OH
Y
V
OL
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 2 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Output current
Maximum power
*1
dissipation
Storage temperature
Note:
Symbol
V
CC
V
I
V
DS
I
DS
P
T
Tstg
Ratings
6.5
–0.5 to V
CC
–0.5 to 15
200
1.47
1.38
0.76
–55 to +125
Unit
V
V
V
mA
W
°C
Conditions
Output : “Z” (off)
Output : “on” , Current of one circuit
SDIP
Ta = 25°C
DILP
Base implementation
TSSOP
The absolute maximum ratings are values which must not individually be exceeded, and furthermore no two of
which may be realized at the same time.
1. The maximum package power dissipation was calculated using a junction temperature of 150°C
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
Output current
(Current of an one circuit,
when eight circuit
operation)
Input rise / fall time
Operating temperature
Note:
Symbol
V
CC
V
I
V
DS
Ratings
3.0
0
0
0
0
0
0
0
0
0
–20
5.5
V
CC
15
200
150
200
140
200
105
500
85
Unit
V
V
V
mA
mA
mA
ns
°C
Conditions
Output “Z” (off)
SDIP
DILP
TSSOP
Duty cycle
≤
60%
Duty cycle
≤
100%
Duty cycle
≤
55%
Duty cycle
≤
100%
Duty cycle
≤
25%
Duty cycle
≤
100%
I
DS
t
r
, t
f
Ta
V
CC
= 3.0 V, 4.5 V
Unused or floating inputs must be held high or low.
Electrical Characteristics
(Ta = –20 to +85°C)
Item
Symbol
V
IH
Input voltage
V
IL
VCC (V)
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
5.5
5.5
I
DS
R
DS
5.0
4.5
Ratings
Min
V
CC
×0.84
V
CC
×0.76
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
0.30
0.25
0.60
0.51
0.005
0.005
0.005
0.005
0.002
2.5
Max
—
—
V
CC
×0.16
V
CC
×0.24
0.45
0.38
0.90
0.77
1.0
–1.0
5.0
5.0
5.0
3.8
µA
Ω
Unit
V
V
I
DS
= 100 mA
V
I
DS
= 200 mA
µA
µA
µA
V
I
= V
CC
V
I
= 0 V
All output “Z” (off)
V
I
= V
CC
or GND
All output “on”, V
I
= V
CC
or GND
V
DS
= 12 V
I
DS
= 100 mA
Conditions
Output voltage
V
DS
“H” input current
“L” input current
Quiescent supply
current
Output off state
leak current
Output on resister
I
IH
I
IL
I
CC
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 3 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Switching Characteristics
(Ta = –20 to +85°C, CL = 30 pF, tr = tf =6 ns )
Item
Maximum clock
frequency
Propagation delay
time
Propagation delay
time
Setup time
Hold time
Pulse width
Output rise time
Output fall time
Symbol
f
max
t
PLH
t
PHL
t
su
t
h
t
W
t
TLH
t
THL
VCC (V)
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
Ratings
Min
—
—
1.0
1.0
1.0
1.0
25
20
3
3
50
40
—
—
—
—
Max
15
20
65
50
60
45
—
—
—
—
—
—
30
20
10
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
CLK,
CLR
to
Y
CLK to
Y
D to CLK
CLK to D
CLK,
CLR
Y
Y
Conditions
Test Circuit
V
CC
Input
V
T
= 12V
V
CC
See Function Table
Palse generator
Z
out
= 50
Ω
CLK
D
CLR
GND
Y
R
L
= 120Ω
Output
Input
Palse generator
Z
out
= 50
Ω
C
L
= 30 pF
Note: 1. Input waveform : PRR = 1MHz, Duty Cycle = 50%, tr = 6ns, tf = 6ns
2. C
L
includes probe and jig capacitance.
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 4 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Waveforms
•
Waveforms – 1
t
r
90 %
90 %
50 %
10 %
50 %
t
f
V
CC
GND
t
h
Data Input (D0 to D7)
10 %
50 %
t
su
t
r
t
h
t
f
90 %
t
su
V
CC
50 %
10 %
Clock Input (CLK)
10 %
50 %
GND
t
PLH
90 %
t
PHL
90 %
50 %
10 %
V
OH
V
OL
Output (Y0 to
Y7)
50 %
10 %
t
THL
t
TLH
t
f
90 %
50 %
10 %
t
PLH
V
CC
GND
•
Waveforms – 2
Clear Input (CLR)
Output (Y0 to
Y7)
90 %
50 %
10 %
t
TLH
V
OH
V
OL
•
Waveforms – 3
t
r
90 %
50 %
10 %
90 %
50 %
10 %
t
f
V
CC
GND
High Level Pulse
t
w
All Input
90 %
t
w
90 %
50 %
10 %
50 %
10 %
V
CC
Low Level Pulse
GND
t
r
t
f
Notes: 1. Input waveform : PRR
≤
1 MHz, Zo = 50
Ω,
t
r
≤
6 ns, t
f
≤
6 ns
2. The input and output is measured one at a time with one transition per measurement.
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 5 of 9
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