TBB1017
Twin Built in Biasing Circuit MOS FET IC
UHF/VHF RF Amplifier
REJ03G1469-0100
Rev.1.00
Aug 07, 2006
Features
•
•
•
•
•
•
•
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
Very useful for total tuner cost reduction.
Suitable for World Standard Tuner RF amplifier.
High gain
Low noise
Low output capacitance
Power supply voltage: 5 V
Outline
RENESAS Package code: PTSP0006JA-A
(Package name: CMPAK-6)
5
4
6
2
1
3
1. Drain(1)
2. Source
3. Gate-1(1)
4. Gate-1(2)
5. Gate-2
6. Drain(2)
Notes:
1. Marking is “SM“.
2. TBB1017 is individual type number of Renesas TWIN BBFET.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Gate2 to source voltage
Symbol
V
DS
V
G1S
V
G2S
Ratings
6
+6
–0
+6
–0
30
250
150
–55 to +150
Unit
V
V
V
mA
mW
°
C
°
C
Drain current
I
D
Channel power dissipation
Pch
Note3
Channel temperature
Tch
Storage temperature
Tstg
Notes: 3. Value on the glass epoxy board (50mm
×
40mm
×
1mm).
Rev.1.00
Aug 07, 2006
page 1 of 13
TBB1017
Electrical Characteristics
•
FET1
(Ta = 25°C)
Item
Drain to source breakdown
voltage
Gate1 to source breakdown
voltage
Gate2 to source breakdown
voltage
Gate1 to source cutoff
current
Gate2 to source cutoff
current
Gate1 to source cutoff
voltage
Gate2 to source cutoff
voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Ciss
Coss
PG
NF
Min
6
+6
+6
—
—
0.5
0.4
12
27
1.3
0.7
15
—
Typ
—
—
—
—
—
0.8
0.7
16
32
1.7
1.1
20
1.95
Max
—
—
—
+100
+100
1.1
1.0
20
38
2.1
1.5
25
2.7
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
dB
dB
Test Conditions
I
D
= 200
µA,
V
G1S
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V, I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V, I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V,
f = 1 kHz, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V,
f = 1 MHz, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V,
R
G
= 100 kΩ, f = 900 MHz
•
FET2
(Ta = 25°C)
Item
Drain to source breakdown
voltage
Gate1 to source breakdown
voltage
Gate2 to source breakdown
voltage
Gate1 to source cutoff
current
Gate2 to source cutoff
current
Gate1 to source cutoff
voltage
Gate2 to source cutoff
voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Ciss
Coss
PG
NF
Min
6
+6
+6
—
—
0.5
0.4
13
25
2.3
0.9
24
—
Typ
—
—
—
—
—
0.8
0.7
17
30
2.7
1.3
29
1.0
Max
—
—
—
+100
+100
1.1
1.0
21
35
3.1
1.7
34
1.6
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
dB
dB
Test Conditions
I
D
= 200
µA,
V
G1s
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V, I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V, I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 82 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V,
f = 1 kHz, R
G
= 82 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V,
f = 1 MHz, R
G
= 82 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V,
R
G
= 82 kΩ, f = 200 MHz
Rev.1.00
Aug 07, 2006
page 2 of 13
TBB1017
DC Biasing Circuit for Operating Characteristic Items (I
D(op)
, |y
fs
|, Ciss, Coss, NF, PG)
•
Measurement of FET1
Gate 2
V
G2
Open
Open
I
D
V
D
A
Drain
Source
Gate 1
R
G
V
G1
•
Measurement of FET2
V
G2
Gate 2
Drain
I
D
V
D
A
Gate 1
R
G
V
G1
Open
Source
Open
Rev.1.00
Aug 07, 2006
page 3 of 13
TBB1017
900 MHz Power Gain, Noise Figure Test Circuit
V
G1
V
G2
C4
C5
V
D
C6
R1
R2
C3
G2
R3
D
L3
RFC
Output
(
50
Ω)
L4
Input
(
50
Ω)
L1
L2
G1
S
C1
C2
C1, C2
C3
C4 ~ C6
R1
R2
R3
:
:
:
:
:
:
Variable Capacitor (10 pF MAX)
Disk Capacitor (1000 pF)
Air Capacitor (1000 pF)
100 kΩ
47 kΩ
4.7 kΩ
L1:
10
10
L2:
26
3
3
(φ 1 mm Copper wire)
Unit: mm
8
21
L4:
29
10
7
7
10
L3:
18
RFC :
φ1
mm Copper wire with enamel 4 turns inside dia 6 mm
Rev.1.00
Aug 07, 2006
page 4 of 13
TBB1017
200 MHz Power Gain, Noise Figure Test Circuit
V
T
1000 p
V
G2
1000 p
V
T
1000 p
47 k
Input (50
Ω)
1000 p
36 p
L1
1000 p
47 k
FET2
L2
1000 p
47 k
Output (50
Ω)
10 p max
1000 p
1SV70
R1
1000 p
V
G1
1000 p
V
D
Unit : Resistance (Ω)
Capacitance (F)
RFC
1SV70
R1 : 82 kΩ
L1 :
φ1
mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns
L2 :
φ1
mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns
RFC :
φ1
mm Enameled Copper Wire, Inside dia 5 mm, 2 Turns
Rev.1.00
Aug 07, 2006
page 5 of 13
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