TBB1010
Twin Built in Biasing Circuit MOS FET IC
VHF/VHF RF Amplifier
REJ03G0844-0500
Rev.5.00
Aug 22, 2006
Features
•
•
•
•
•
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
High |yfs|=29mS
×
2
Suitable for World Standard Tuner RF amplifier.
Very useful for total tuner cost reduction.
Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200 V at C = 200 pF,
Rs = 0 conditions.
•
Provide mini mold packages; CMPAK-6
Outline
RENESAS Package code: PTSP0006JA-A
(Package name: CMPAK-6)
6
5
4
2
1
3
1. Drain(1)
2. Source
3. Drain(2)
4. Gate-1(2)
5. Gate-2
6. Gate-1(1)
Notes:
1. Marking is “KM”.
2. TBB1010 is individual type number of RENESAS TWIN BBFET.
Rev.5.00 Aug 22, 2006 page 1 of 7
TBB1010
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Gate2 to source voltage
Symbol
V
DS
V
G1S
V
G2S
Ratings
6
+6
-0
+6
-0
30
250
150
–55 to +150
Unit
V
V
V
mA
mW
°C
°C
Drain current
I
D
Channel power dissipation
Pch
*3
Channel temperature
Tch
Storage temperature
Tstg
Notes: 3. Value on the glass epoxy board (50mm
×
40mm
×
1mm).
Electrical Characteristics
(Ta = 25°C)
The below specification are applicable for FET1 and FET2 unit
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Ciss
Coss
Crss
PG
NF
Min
6
+6
+6
—
—
0.6
0.6
12
24
1.7
1.0
—
25
—
Typ
—
—
—
—
—
—
—
16
29
2.1
1.4
0.03
30
1.1
Max
—
—
—
+100
+100
1.1
1.1
20
—
2.5
1.8
0.05
—
1.8
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
pF
dB
dB
Test conditions
I
D
= 200
µA,
V
G1S
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V,
I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V,
I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 120 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 120 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 120 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 120 kΩ, f = 200 MHz
Rev.5.00 Aug 22, 2006 page 2 of 7
TBB1010
Test Circuits
•
DC Biasing Circuit for Operating Characteristic Items
(I
D(op)
, |yfs|, Ciss, Coss, Crss, NF, PG)
Measurment of FET1
R
G
V
G1
Gate 1
Gate 2
Open
V
G2
I
D
V
D
A
Drain
Source
Open
Measurment of FET2
Gate 2
V
G2
Open
V
G1
Gate 1
R
G
A
Open
Source
Drain
I
D
V
D
Rev.5.00 Aug 22, 2006 page 3 of 7
TBB1010
•
Equivalent Circuit
No.1
Drain(1)
No.6
Gate-1(1)
No.2
Source
BBFET-(1)
BBFET-(2)
No.3
Drain(2)
No.5
Gate-2
No.4
Gate-1(2)
•
200 MHz Power Gain, Noise Figure Test Circuit
V
T
1000p
V
G2
1000p
V
T
1000p
47k
Input (50
Ω)
1000p
36p
L1
1000p
47k
TWINBBFET
L2
1000p
47k
Output (50
Ω)
10p max
1000p
1SV70
R
G
120k
RFC
1SV70
1000p
V
D
= V
G1
Unit : Resistance (Ω)
Capacitance (F)
L1 :
φ1mm
Enameled Copper Wire,Inside dia 10mm, 2Turns
L2 :
φ1mm
Enameled Copper Wire,Inside dia 10mm, 2Turns
RFC :
φ1mm
Enameled Copper Wire,Inside dia 5mm, 2Turns
Rev.5.00 Aug 22, 2006 page 4 of 7
TBB1010
Maximum Channel Power
Dissipation Curve
Channel Power Dissipation Pch* (mW)
400
25
V
G2S
= 4 V
V
G1
= V
DS
R
82
G
=
Typical Output Characteristics
Drain Current I
D
(mA)
300
10
12
0
15
200
10
0
15
0
18
100
5
0
50
100
150
200
0
1
2
3
4
k
Ω
0k
Ω
20
k
Ω
k
Ω
k
Ω
5
Ambient Temperature Ta (°C)
* Value on the glass epoxy board (50mm
× 40mm ×
1mm)
Drain to Source Voltage V
DS
(V)
Drain Current vs. Gate1 Voltage
25
V
DS
= 5 V
R
G
= 120 kΩ
4V
Forward Transfer Admittance
vs. Gate1 Voltage
Forward Transfer Admittance |y
fs
| (mS)
50
V
DS
= 5 V
R
G
= 120 kΩ
40 f = 1 kHz
30
4V
Drain Current I
D
(mA)
20
15
3V
3V
10
2V
20
2V
5
V
G2S
= 1 V
10
V
G2S
= 1 V
0
1
2
3
4
5
0
1
2
3
4
5
Gate1 Voltage V
G1
(V)
Gate1 Voltage V
G1
(V)
Input Capacitance vs.
Gate2 to Source Voltage
4
Drain Current vs. Gate Resistance
30
25
Input Capacitance Ciss (pF)
Drain Current I
D
(mA)
V
DS
= 5 V
V
G1
= 5 V
V
G2S
= 4 V
3
20
15
10
5
0
10
2
V
DS
= 5 V
V
G1
= 5 V
R
G
= 120 kΩ
f = 1 MHz
0
1
2
3
4
1
0
20
50
100 200
500 1000
Gate Resistance R
G
(kΩ)
Gate2 to Source Voltage V
G2S
(V)
Rev.5.00 Aug 22, 2006 page 5 of 7
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