TBB1004
Twin Built in Biasing Circuit MOS FET IC
VHF/UHF RF Amplifier
REJ03G0842-1100
Rev.11.00
Aug 22, 2006
Features
•
•
•
•
•
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
Suitable for World Standard Tuner RF amplifier.
Very useful for total tuner cost reduction.
Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions.
Provide mini mold packages; CMPAK-6
Outline
RENESAS Package code: PTSP0006JA-A
(Package name: CMPAK-6)
6
5
4
2
1
3
1. Drain(1)
2. Source
3. Gate-1(1)
4. Gate-1(2)
5. Gate-2
6. Drain(2)
Notes:
1. Marking is “DM”.
2. TBB1004 is individual type number of RENESAS TWIN BBFET.
Rev.11.00 Aug 22, 2006 page 1 of 9
TBB1004
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Gate2 to source voltage
Symbol
V
DS
V
G1S
V
G2S
Ratings
6
+6
-0
+6
-0
30
250
150
–55 to +150
Unit
V
V
V
mA
mW
°C
°C
Drain current
I
D
Channel power dissipation
Pch
*3
Channel temperature
Tch
Storage temperature
Tstg
Note: 3. Value on the glass epoxy board (49mm
×
38mm
×
1mm).
Electrical Characteristics
(Ta = 25°C)
The below specification are applicable for UHF unit (FET1)
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Ciss
Coss
Crss
PG
NF
Min
6
+6
+6
—
—
0.5
0.5
13
21
1.4
1.0
—
16
—
Typ
—
—
—
—
—
0.7
0.7
17
26
1.8
1.4
0.02
21
1.7
Max
—
—
—
+100
+100
1.0
1.0
21
31
2.2
1.8
0.04
—
2.5
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
pF
dB
dB
Test conditions
I
D
= 200
µA,
V
G1S
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V
I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V
I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
=4 V, R
G
= 100 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 900 MHz
Zi = S11*, Zo = S22*(:PG)
Zi = S11opt (:NF)
Rev.11.00 Aug 22, 2006 page 2 of 9
TBB1004
Electrical Characteristics
(cont.)
(Ta = 25°C)
The below specification are applicable for VHF unit (FET2)
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Ciss
Coss
Crss
PG
NF
Min
6
+6
+6
—
—
0.5
0.5
16
27
2.3
1.4
—
24
—
Typ
—
—
—
—
—
0.75
0.75
20
32
2.7
1.8
0.03
29
1.2
Max
—
—
—
+100
+100
1.0
1.0
24
37
3.1
2.2
0.05
—
1.7
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
pF
dB
dB
Test conditions
I
D
= 200
µA,
V
G1S
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V
I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V
I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 200 MHz
Rev.11.00 Aug 22, 2006 page 3 of 9
TBB1004
Test Circuits
•
DC Biasing Circuit for Operating Characteristic Items
(I
D(op)
, |yfs|, Ciss, Coss, Crss, NF, PG)
Measurment of FET1
Gate 2
V
G2
Open
Open
I
D
V
D
A
Drain
Source
Gate 1
R
G
V
G1
Measurment of FET2
V
G2
Gate 2
Drain
I
D
V
D
A
Gate 1
R
G
V
G1
Open
Source
Open
Rev.11.00 Aug 22, 2006 page 4 of 9
TBB1004
•
Equivalent Circuit
No.1
Drain(1)
BBFET-(1)
No.2
Source
BBFET-(2)
No.5
Gate-2
No.6
Drain(2)
No.3
Gate-1(1)
No.4
Gate-1(2)
•
200 MHz Power Gain, Noise Figure Test Circuit
V
T
1000p
V
G2
1000p
V
T
1000p
47k
Input (50Ω)
L1
1000p
36p
1000p
47k
TWINBBFET
L2
1000p
47k
Output (50Ω)
10p max
1000p
1SV70
R
G
100k
RFC
1SV70
1000p
V
D
= V
G1
Unit : Resistance (Ω)
Capacitance (F)
L1 :
φ1mm
Enameled Copper Wire,Inside dia 10mm, 2Turns
L2 :
φ1mm
Enameled Copper Wire,Inside dia 10mm, 2Turns
RFC :
φ1mm
Enameled Copper Wire,Inside dia 5mm, 2Turns
Rev.11.00 Aug 22, 2006 page 5 of 9
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