SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064
SST58LD008 / 016 / 024 / 032 / 048 / 064
Preliminary Specifications
FEATURES:
• ATA/IDE standard interface
– 512 Bytes per sector
– ATA command set compatible
– Support Data Transfer Speed up to PIO Mode-3
• 8, 16, 24, 32, 48 and 64 MByte capacities
• Standard 600mil 32pin DIP package
• Single Voltage Read and Write Operation
– 5.0 Volt-only for SST58SDxxx
– 3.3 Volt-only for SST58LDxxx
• Supports 5.0-Volt or 3.3-Volt Read and Write
– 5V + 10% or 3.3V + 5% for Commercial
– 5V + 5% or 3.3V + 5% for Industrial
• Low Power Consumption:
– Active mode: 30mA/50mA (3.3V/5.0V) (typical)
– Sleep mode: 200µA/600µA (3.3V/5.0V) (maximum)
• Data Transfer Rate to/from Host
– 20 MB/s burst at 5.0 V
– 6.6 MB/s burst at 3.3 V
• Sustained Write Performance
– Up to 1.4MB/sec (host to flash)
• Controller Overhead Command to DRQ
– Less than 0.5 ms
• Zero Power Data Retention
– Batteries not required for data storage
• Start Up Time
– Sleep to read: 200 ns (typical)
– Sleep to write: 200 ns (typical)
– Power-on to Ready: 200 ms (typical),
500 ms (maximum)
• Support for Both Commercial and Industrial
Temperature Range
– 0°C to 70°C for Operating Commercial
– -40 °C to +85 °C for Operating Industrial
– -50 °C to +100 °C for non-Operating (storage)
• Extremely Rugged and Reliable
– Built-in ECC support corrects 3 Bytes
of error per 512 Byte sector
– Endurance: 1,000,000 cycles (typical)
– Greater than 1,000,000 hours MTBF
• Intelligent ATA/IDE Controller
– Built-in microcontroller with intelligent firmware
– Built-in Flash File System
• Power Management Unit
– Immediate disabling of unused circuitry
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Product Description
SST’s ATA-Disk Chip (ADC) is a low cost, high perfor-
mance, embedded flash memory data storage system.
This product is well suited for solid state mass storage
applications offering new and expanded functionality
while enabling cost effective designs.
ATA-based solid state mass storage technology is
widely used in such products as portable and desktop
computers, digital cameras, music players, handheld
data collection scanners, cellular phones, PCS phones,
PDAs, handy terminals, personal communicators, ad-
vanced two-way pagers, audio recorders, monitoring
devices, and set-top boxes.
ADC provides complete IDE Hard Disk Drive function-
ality and compatibility. ADC is a perfect solution to
consumer electronic products requiring smaller, but
more reliable and cost effective data storage. The ADC
is read and written using a single power supply of 5.0-
Volts or 3.3-Volts and is available in 8, 16, 24, 32, 48 and
64 MByte capacities.
The ADC is a solid state disk drive that is designed to
replace conventional IDE hard disk drive and uses
standard ATA/IDE protocol. It has built in
microcontroller and file management firmware that
communicates with ATA standard interfaces; therefore,
the ADC does not require additional or proprietary
software such as Flash File System (FFS) and Memory
Technology Driver (MTD) software.
The ADC is designed to work at either 5V ±10% or 3.3V
±5%. The pin assignment is designed to match existing
IDE signal traces on the motherboard. It uses standard
ATA driver that is part of all major OS such as Windows
95/98/2000/NT/CE, MAC, UNIX, etc.
The ADC is packaged in the standard 600 mil. 32-pin
DIP package for easy and cost effective mounting to the
system motherboard.
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© 2000 Silicon Storage Technology, Inc.
391-2 8/00
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ATA-Disk Chip is
a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
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SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064
SST58LD008 / 016 / 024 / 032 / 048 / 064
Preliminary Specifications
Table of Contents
Product Description ................................................................................................................. 1
1.0 General Description ........................................................................................................... 5
1.1 Optimized for performance ATA Controller ...................................................................................................
1.1.1 Microcontroller Unit (MCU) ....................................................................................................................
1.1.2 Internal Direct Memory Access (DMA) ..................................................................................................
1.1.3 Power Management Unit (PMU) .............................................................................................................
1.1.4 SRAM Buffer ...........................................................................................................................................
1.1.5 Firmware Storage ..................................................................................................................................
1.2 SST’s ADC Product Offering ............................................................................................................................
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2.0 Electrical Interface .............................................................................................................. 6
2.0.1 Pin Assignment and Pin Type ................................................................................................................ 6
2.1 Electrical Description ....................................................................................................................................... 6
2.2 Absolute Maximum Stress Ratings ................................................................................................................ 9
2.3 Electrical Specification .................................................................................................................................. 10
2.3.1 Absolute Maximum Conditions .......................................................................................................... 10
2.3.2 Input Leakage Current .......................................................................................................................... 11
2.3.3 Input Characteristics ............................................................................................................................. 11
2.3.4 Output Drive Type ................................................................................................................................. 11
2.3.5 Output Drive Characteristics ................................................................................................................ 11
2.3.6 I/O Input (Read) Timing Specification .................................................................................................. 12
2.3.7 I/O Output (Write) Timing Specification ............................................................................................... 13
2.4 I/O Transfer Function ..................................................................................................................................... 14
2.4.1 I/O Function .......................................................................................................................................... 14
3.0 Software Interface ............................................................................................................. 15
3.1 ADC Drive Register Set Definitions and Protocol .........................................................................................
3.1.1 ADC Addressing ....................................................................................................................................
3.1.2 ADC Registers .......................................................................................................................................
3.1.2.1 Data Register ......................................................................................................................................
3.1.2.2 Error Register (Read Only) ................................................................................................................
3.1.2.3 Feature Register (Write Only) ............................................................................................................
3.1.2.4 Sector Count Register .......................................................................................................................
3.1.2.5 Sector Number (LBA 7-0) Register ....................................................................................................
3.1.2.6 Cylinder Low (LBA 15-8) Register .....................................................................................................
3.1.2.7 Cylinder High (LBA 23-16) Register ...................................................................................................
3.1.2.8 Drive/Head (LBA 27-24) Register .......................................................................................................
3.1.2.9 Status & Alternate Status Registers (Read Only) ..............................................................................
3.1.2.10 Device Control Register (Write Only) ..............................................................................................
3.1.2.11 Drive Address Register (Read Only) ................................................................................................
3.1.2.12 Command Register (Write Only) ......................................................................................................
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© 2000 Silicon Storage Technology, Inc.
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391-2 8/00
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064
SST58LD008 / 016 / 024 / 032 / 048 / 064
Preliminary Specifications
3.2 ADC Command Description ...........................................................................................................................
3.2.1 ADC Command Set ...............................................................................................................................
3.2.1.1 Check Power Mode - 98h or E5h .......................................................................................................
3.2.1.2 Execute Drive Diagnostic - 90h .........................................................................................................
3.2.1.3 Format Track - 50h .............................................................................................................................
3.2.1.4 Identify Drive - ECh ............................................................................................................................
3.2.1.4.1 General Configuration ....................................................................................................................
3.2.1.4.2 Default Number of Cylinders ..........................................................................................................
3.2.1.4.3 Default Number of Heads ................................................................................................................
3.2.1.4.4 Number of Unformatted Bytes per Track ........................................................................................
3.2.1.4.5 Number of Unformatted Bytes per Sector ......................................................................................
3.2.1.4.6 Default Number of Sectors per Track .............................................................................................
3.2.1.4.7 Number of Sectors ..........................................................................................................................
3.2.1.4.8 Memory Serial Number ...................................................................................................................
3.2.1.4.9 Buffer Type ......................................................................................................................................
3.2.1.4.10 Buffer Size .....................................................................................................................................
3.2.1.4.11 ECC Count .....................................................................................................................................
3.2.1.4.12 Firmware Revision ........................................................................................................................
3.2.1.4.13 Model Number ...............................................................................................................................
3.2.1.4.14 Read/Write Multiple Sector Count ................................................................................................
3.2.1.4.15 Double Word Support ...................................................................................................................
3.2.1.4.16 Capabilities ....................................................................................................................................
3.2.1.4.17 PIO Data Transfer Cycle Timing Mode .........................................................................................
3.2.1.4.18 DMA Data Transfer Cycle Timing Mode ........................................................................................
3.2.1.4.19 Translation Parameters Valid ........................................................................................................
3.2.1.4.20 Current Number of Cylinders, Heads, Sectors/Track ...................................................................
3.2.1.4.21 Current Capacity ............................................................................................................................
3.2.1.4.22 Multiple Sector Setting .................................................................................................................
3.2.1.4.23 Total Sectors Addressable in LBA Mode .....................................................................................
3.2.1.4.24 Advanced PIO Data Transfer Mode ...............................................................................................
3.2.1.4.25 Minimum PIO Transfer Cycle Time Without Flow Control ..........................................................
3.2.1.4.26 Minimum PIO Transfer Cycle Time With IORDY ..........................................................................
3.2.1.5 Idle - 97h or E3h .................................................................................................................................
3.2.1.6 Idle Immediate - 95h or E1h ..............................................................................................................
3.2.1.7 Initialize Drive Parameters - 91h .......................................................................................................
3.2.1.8 Read Buffer - E4h ...............................................................................................................................
3.2.1.9 Read Multiple - C4h ............................................................................................................................
3.2.1.10 Read Long Sector - 22h or 23h ........................................................................................................
3.2.1.11 Read Sector(s) - 20h or 21h .............................................................................................................
3.2.1.12 Read Verify Sector(s) - 40h or 41h ...................................................................................................
3.2.1.13 Recalibrate - 1Xh ..............................................................................................................................
3.2.1.14 Seek - 7Xh ........................................................................................................................................
3.2.1.15 Set Features - EFh ............................................................................................................................
3.2.1.16 Set Multiple Mode - C6h ..................................................................................................................
3.2.1.17 Set Sleep Mode- 99h or E6h ............................................................................................................
3.2.1.18 Standby - 96h or E2h .......................................................................................................................
3.2.1.19 Standby Immediate - 94h or E0h .....................................................................................................
3.2.1.20 Write Buffer - E8h .............................................................................................................................
3.2.1.21 Write Long Sector - 32h or 33h ........................................................................................................
3.2.1.22 Write Multiple Command - C5h .......................................................................................................
3.2.1.24 Write Verify - 3Ch ..............................................................................................................................
3.2.1.23 Write Sector(s) - 30h or 31h .............................................................................................................
3.2.2 Error Posting .........................................................................................................................................
© 2000 Silicon Storage Technology, Inc.
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391-2 8/00
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064
SST58LD008 / 016 / 024 / 032 / 048 / 064
Preliminary Specifications
4.0 Appendix ........................................................................................................................... 40
4.1 Differences between ADC and ATA/ATAPI-5 Specifications .........................................................................
4.1.1 Electrical Differences ............................................................................................................................
4.1.1.1 TTL Compatibility ..............................................................................................................................
4.1.1.2 Pull Up Resistor Input Leakage Current ...........................................................................................
4.1.2 Functional Differences ..........................................................................................................................
4.1.2.1 Set Features Codes not Supported in ATA/ATAPI-5 Specifications .................................................
4.1.2.2 Additional Set Features Codes in ADC .............................................................................................
4.1.2.3 Idle Timer ...........................................................................................................................................
4.1.2.4 Recovery from Sleep Mode ...............................................................................................................
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5.0 Physical Dimensions ........................................................................................................ 41
Ordering Information ...........................................................................................................................................
Valid combinations ..............................................................................................................................................
Limited Warranty ..................................................................................................................................................
Life Support Policy ..............................................................................................................................................
Patent Protection .................................................................................................................................................
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© 2000 Silicon Storage Technology, Inc.
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391-2 8/00
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064
SST58LD008 / 016 / 024 / 032 / 048 / 064
Preliminary Specifications
1.0 General Description
The SST’s ATA-Disk Chip (ADC) contains a controller,
embedded firmware and flash media in a 32-pin DIP
package. Refer to Figure 1-1 for SST’s ADC block
diagram. The controller interfaces with the host system
allowing data to be written to and read from the flash
media.
1.1 Optimized for performance ATA Controller
The heart of the ADC is the ATA controller which trans-
lates standard ATA signals into Flash media data and
controls. SST’s ADC contains a proprietary ATA control-
ler that was specifically designed to attain high data
throughput from host to Flash. The following components
contribute to the ATA controller’s performance.
1.1.1 Microcontroller Unit (MCU)
The MCU translates ATA commands into data and control
signals required for flash memory operation.
1.1.2 Internal Direct Memory Access (DMA)
The ATA controller inside ADC uses DMA allowing instant
data transfer from buffer to memory. This implementation
eliminates microcontroller overhead associated with tra-
ditional, firmware based, memory control, increasing data
transfer rate.
1.1.3 Power Management Unit (PMU)
Power Management Unit controls the power consumption
of the ADC. The PMU dramatically extends product
battery life by putting the part of the circuitry that is not
in operation into sleep mode.
1.1.4 SRAM Buffer
A key contributor to the ATA controller performance is a
SRAM buffer. The buffer optimizes the data writes to
Flash.
1.1.5 Firmware Storage
Firmware Storage is embedded within the ATA controller
for optimum data transfer performance.
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ATA Controller
Firmware
Storage
MCU
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SRAM Buffer
HOST
Internal
DMA
Flash
Media
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PMU
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391 ILL1-1.2
F
IGURE
1-1: SST ADC B
LOCK
D
IAGRAM
© 2000 Silicon Storage Technology, Inc.
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391-2 8/00
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