TSPC2605
INTEGRATED SECONDARY CACHE MODULE
FOR PowerPCt MICROPROCESSORS
DESCRIPTION
The TSPC2605 is a single chip, 256KB integrated look–aside
cache with copy–back capability designed for PowerPC
applications (TSPC603e). Using 0.38
µm
technology along
with standard cell logic technology, the TSPC2605 integrates
data, tag, host interface, and least recently used (LRU)
memory with a cache controller to provide a 256KB, 512KB, or
1 MB Level 2 cache with one, two, or four chips on a 64–bit
PowerPC bus.
MAIN FEATURES
H
Single Chip L2 Cache for PowerPC
H
66 MHz Zero Wait State Performance (2–1–1–1 Burst)
H
Four–Way Set Associative Cache Design
H
32K x 72 Data Memory Array
H
8K x 18 Tag Array
H
Address Parity Support
H
LRU Cache Control Logic
H
Copy–Back or Write–Through Modes of Operation
H
Copy–Back Buffer for Improved Performance
H
Single 3.3 V Power Supply
H
5 V Tolerant I/O
H
1, 2, or 4 Chip Cache Solution (256KB, 512KB, or 1MB)
H
Single Clock Operation
H
Compliant with IEEE Standard 1149.1 Test Access Port
(JTAG)
H
Supports up to 4 Processors in a Shared Cache
Configuration
PBGA 241
ZP suffix
Plastic Ball Grid Array
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
CBGA 241
G suffix
Ceramic Ball Grid Array
(To be introduced)
H
MIL-STD-883 class B or According to TCS standards
H
Upscreening based upon TCS standards
H
Full military temperature range (T
c
= -55°C, Tc = +125°C)
Industrial temperature range
H
Power Supply = 3.3 V
±
5 %.
(T
c
=
–
40°C, T
c
= +110°C)
H
241–pin PBGA and CBGA packages
May 1998
1/36
TSPC2605
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3
1. PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 4
3. SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . 6
5.4.3.Data Streaming . . . . . . . . . . . . . . . . . . . . . .
5.4.4.Data Bus Parking . . . . . . . . . . . . . . . . . . . .
5.4.5.Processor Reads . . . . . . . . . . . . . . . . . . . . .
5.4.6.Processor Writes . . . . . . . . . . . . . . . . . . . . .
5.4.7.Transaction Pipelining . . . . . . . . . . . . . . . .
15
15
15
16
16
5.5. Memory coherence . . . . . . . . . . . . . . . . . . . . 16
B. DETAILED SPECIFICATIONS . . . . . . . . . . . 7
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . 7
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2. Design and construction . . . . . . . . . . . . . . . . . 7
3.2.1.Terminal connections . . . . . . . . . . . . . . . . .
3.2.2.Lead material and finish . . . . . . . . . . . . . . .
3.2.3.Hermetic Package . . . . . . . . . . . . . . . . . . . .
7
7
7
5.5.1.Snoop Reads . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5.2.Snoop Writes . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5.3.Snoop Kills . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6. Two/Four Chip Implementation . . . . . . . . . . 17
5.6.1.Multiple Castouts . . . . . . . . . . . . . . . . . . . . . 17
5.6.2.Snoop Hit Before Castout . . . . . . . . . . . . . 17
5.7. Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . 17
5.8. Powering–Down . . . . . . . . . . . . . . . . . . . . . . . 17
5.9. Asynchronous signals . . . . . . . . . . . . . . . . . . 17
5.9.1.L2 FLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.2.L2 MISS INH . . . . . . . . . . . . . . . . . . . . . . . .
5.9.3.L2 TAG CLR . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.4.L2 UPDATE INH . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
3.3. Absolute maximum ratings . . . . . . . . . . . . . . . 7
3.4. Thermal Characteristics . . . . . . . . . . . . . . . . . 7
3.4.1.PBGA Package . . . . . . . . . . . . . . . . . . . . . .
3.4.2.CBGA Package . . . . . . . . . . . . . . . . . . . . . .
7
8
3.5. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . 9
4.1. Recommanded Operating Conditions . . . . . . 9
4.2. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 9
4.3. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4. AC Operating Conditions . . . . . . . . . . . . . . . 10
4.4.1.AC Clock Specification . . . . . . . . . . . . . . . .
4.4.2.AC Specifications . . . . . . . . . . . . . . . . . . . .
4.4.3.Response to 60X Transfer Attributes . . . .
4.4.4.Response to Chipset Transfer Attributes .
4.4.5.Transfer Attributes for L2 Copy–Back . . .
10
10
11
11
11
5.10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.11. Test Access Port Description . . . . . . . . . . . . 28
5.11.1.Instruction Set . . . . . . . . . . . . . . . . . . . . . .
5.11.2.Standard Instructions . . . . . . . . . . . . . . . .
5.11.3.SAMPLE/PRELOAD TAP Instruction . . .
5.11.4.EXTEST TAP Instruction . . . . . . . . . . . . .
5.11.5.CLAMP TAP Instruction . . . . . . . . . . . . . .
5.11.6.HIGHZ TAP Instruction . . . . . . . . . . . . . . .
5.11.7.BYPASS TAP Instruction . . . . . . . . . . . . .
5.11.8.Disabling the TAP and Boundary Scan .
28
28
28
28
28
28
28
29
5.12.Boundary Scan Order . . . . . . . . . . . . . . . . . . 30
5.12.1.Bit number . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.2.Bit/pin name . . . . . . . . . . . . . . . . . . . . . . . .
5.12.3.Bit/pin type . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.4.Output enable . . . . . . . . . . . . . . . . . . . . . .
30
30
30
30
4.5. JTAG AC Operating Conditions . . . . . . . . . . 12
4.5.1.TAP Controller Timing . . . . . . . . . . . . . . . . . 12
5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 13
5.1. System Usage and Requirments . . . . . . . . . 13
5.1.1.Comprehension of L2 CLAIM . . . . . . . . . . 13
5.1.2.Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3.Bus mastering . . . . . . . . . . . . . . . . . . . . . . . 13
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 33
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2. Certificate of compliance . . . . . . . . . . . . . . . . 33
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . 34
8.1. 241 pins – PBGA . . . . . . . . . . . . . . . . . . . . . . 34
8.2. 241 pins – CBGA . . . . . . . . . . . . . . . . . . . . . . 35
9. ORDERING INFORMATION . . . . . . . . . . . . . . . . 36
5.2. Configuration pins . . . . . . . . . . . . . . . . . . . . . 13
5.2.1.CFG0 – CFG2 . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2.CFG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.3.CFG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3. Reset/Initialization . . . . . . . . . . . . . . . . . . . . . 14
5.4. 60X bus operation . . . . . . . . . . . . . . . . . . . . . 14
5.4.1.Address Tenures . . . . . . . . . . . . . . . . . . . . . 14
5.4.2.Data Tenures . . . . . . . . . . . . . . . . . . . . . . . . 15
2/36
TSPC2605
A. GENERAL DESCRIPTION
1. PIN ASSIGNMENT
1
A
B
C
D
E
TA
F
G
H
J
K
L
M
TT
3
N
P
R
T
U
V
W
CPU
BG
CLK
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
A28
A31
A10
A7
V
SS
V
SS
DH3
DH2
V
SS
DH1
V
SS
DP1
V
SS
V
DD
V
DD
V
DD
DL4
DL3
DL2
V
SS
V
SS
DL6
DL5
V
SS
V
SS
DP4
DL7
V
SS
V
DD
DP5
V
DD
V
DD
A27
A30
A11
A8
A5
A3
A26
A29
A12
A9
A6
A4
A2
L2 DBG CPU2
BG
2
3
4
5
6
7
8
9
10
11
12
13
14
DP6
15
16
17
18
19
ABB L2 BG DH20 DH19 DH17 DH31 DH29 DH27
DH26 DL16 DL19 DL22
DL25 DL27 DL29 DL30
DL28 DL31 DP7
V
DD
AP3
AP0
AP2
L2
FLUSH
APE
AP1
L2
CI
CPU3 CFG4 L2 DH23 DH21 DH18 DH16 DH30 DH28 DH25 DL17 DL20 DL23
MISS INH
BG
FDN CPU3
BR
L2 BR CPU2
BR
CPU3 V
DD
DBG
CPU2
DBG
DP2
DH22 V
SS
V
SS
DP3
V
SS
V
SS
DH24 DL18 DL21 V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
DL24 DL26
V
SS
V
DD
CFG3 APEN GBL
TSIZ1 TSIZ0 TSIZ2
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
D
D
L2
CPU
NC
DBG CLAIM
ARTRY
TEA
CI
CPU
BR
AAC
K
WT
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
A14
A19
A20
A25
V
SS
A15
A18
A22
A24
A13
A16
A17
A21
A23
HRESET DBB PWRDN V
DD
TT1
TT4
TT0
TT2
TBST V
DD
TS
V
DD
V
DD
V
DD
SRESET L2 L2 UPDATE
SS
V
TAG CLR INH
TDI
TDO
TCK
TRST
TMS
NC
V
DD
V
DD
V
DD
DH7
DH6
DH5
DH4
CPU4 CPU4
BG
DBG
CPU4
BR
CFG0
DH14 DH10 DL1
DH13 DH11 DL0
CFG2 CFG1
DP0
DL10 DL12 DL14 DL15 A1
DL8
DL9
DL11 DL13 A0
DH0 DH15 DH12 DH9 DH8
TOP VIEW (X–RAY VIEW)
3/36
TSPC2605
2. SIGNAL DESCRIPTION
Pin Locations
19G, 17H – 19H, 17J – 19J, 17K –
19K, 17L – 19L,17M – 19M, 17N –
19N,17P – 19P, 17R – 19R,18T,
19T, 18U, 19U,18V, 19V, 18W
*
3G
2A
AACK
ABB
I/O
I/O
I/O
O
I
I/O
I
Address acknowledge input/output.
Used as an input to qualify bus grants. Driven as an output during address tenure
initiated by the TSPC2605.
Address parity.
Address parity error. When an address parity error is detected, APE will be driven
low one clock cycle after the assertion of TS then High–Z following clock cycle.
Address parity enable. When tied low, enables address parity bits and the
address parity error bit.
Address retry status I/O. Generated when a read or write snoop to a dirty
processor cache line has occurred.
Configuration inputs. These must be tied to either V
DD
or V
SS
.
CFG0
CFG1
CFG2
0
0
0
256KB
0
1
0
512KB; A26 = 0
0
1
1
512KB; A26 = 1
1
0
0
1MB; A25 – A26 = 00
1
0
1
1MB; A25 – A26 = 01
1
1
0
1MB; A25 – A26 = 10
1
1
1
1MB; A25 – A26 = 11
CFG3
Snoop Data Tenure Selector
0
Supports snoop data tenure
1
Does not support snoop data tenure
AACK Driver Enable
0
Disable AACK driver
1
Enable AACK driver
Pin Name
A0 – A31
Type
I/O
Description
Address inputs from processor. Can also be outputs for processor snoop
addresses. A0 is the MSB. A31 is the LSB.
17C – 19C, 17D
19B
18E
1G
2U
2V
1V
17E
2B
*
AP0 – AP3
APE
APEN
ARTRY
CFG0
CFG1
CFG2
CFG3
CFG4
CFG4
2G
3M
2M
3E
1B
1T
2H
2D
2C
1U
1F
3D
3C
CI
CLK
CPU BG
CPU2 BG
CPU3 BG
CPU4 BG
CPU BR
CPU2 BR
CPU3 BR
CPU4 BR
CPU DBG
CPU2 DBG
CPU3 DBG
I/O
I
I
I
I
I
I
I
I
I
I
I
I
Cache inhibit I/O.
Clock input. This must be the same as the processor clock input.
CPU bus grant input.
TSPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the second CPU BG.
TSPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the third CPU BG.
TSPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the fourth CPU BG.
CPU bus request input.
TSPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the second CPU BR.
TSPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the third CPU BR.
TSPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the fourth CPU BR.
CPU data bus grant input from arbiter.
TSPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the second CPU DBG.
TSPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the third CPU DBG.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
4/36
TSPC2605
Pin Locations
2T
11A – 13A, 15A – 18A,11B – 17B,
11C, 12C, 10U,11U, 10V – 12V,
14V – 17V, 11W – 17W
*
4A – 10A, 4B – 10B, 6C,10C, 8U,
9U, 3V – 6V,8V, 9V, 3W –10W
*
2J
DBB
I/O
Data bus busy. Used as input when processor is master, driven as an output after
a qualified L2 DBG when TSPC2605 is the bus master. Note: To operate in Fast
L2 mode, this pin must be tied high.
Data bus parity input and output.
DH0 – DH31
I/O
Data bus high input and output. DH0 is the MSB. DH31 is the LSB.
Pin Name
CPU4 DBG
DL0 – DL31
Type
I
I/O
Description
TSPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the fourth CPU DBG.
Data bus low input and output. DL0 is the MSB. DL31 is the LSB.
14A, 18B, 5C, 8C,16U, 7V, 13V,
2W
*
1C
19E
1J
DP0 – DP7
I/O
FDN
GBL
HRESET
I/O
O
I
Flush done I/O used for communication between other TSPC2605 devices. Must
be tied together between all TSPC2605 parts along with a pullup resistor.
Global transaction. Always negated when MPC2604 is bus master.
Hard reset input from processor bus. This is an asynchronous input that must be
low for at least 16 clock cycles to ensure the TSPC2605 is properly reset. For
proper initialization, TRST must be asserted before HRESET is asserted.
Bus grant input from arbiter.
Bus request I/O. Normally used as an output.
Secondary cache inhibit sampled, after assertion of TS. Assertion prevents
linefill.
L2 cache claim output. Used to claim the bus for processor initiated memory
operations that hit the L2 cache. L2 CLAIM goes true (low) before the rising edge
of CLK following TS true. Because this output is not always driven, a pullup
resistor may be necessary to ensure proper system functioning.
Data bus grant input. Comes from system arbiter, used to start data tenure for
bus operations where TSPC2605 is the bus master.
Causes cache to write back dirty lines and clears all tag valid bits.
Prevents line fills on misses when asserted.
Invalidates all tags and holds cache in a reset condition.
Cache disable. When asserted, the TSPC2605 will not respond to signals on the
local bus and internal states do not change.
Provides low power mode. Prevents address and data transitions into the RAM
array. TSPC2605 becomes active 4
µs
after deassertion. Clock must be
externally disabled.
Soft reset input from processor bus.
Transfer acknowledge status I/O from processor bus.
Transfer burst status I/O from processor bus. Used to distinguish between
burstable and non–burstable memory operations.
Test clock input for IEEE 1149.1 boundary scan (JTAG).
Test data input for IEEE 1149.1 boundary scan (JTAG).
Test data output for IEEE 1149.1 boundary scan (JTAG).
Transfer error acknowledge status input from processor bus.
Test mode select for IEEE 1149.1 boundary scan (JTAG).
3A
1D
19D
2F
L2 BG
L2 BR
L2 CI
L2 CLAIM
I
I/O
I
O
2E
18D
3B
2N
3N
3J
L2 DBG
L2 FLUSH
L2 MISS INH
L2 TAG CLR
L2 UPDATE
INH
PWRDN
I
I
I
I
I
I
1N
1E
3K
2P
1P
1R
1H
3P
SRESET
TA
TBST
TCK
TDI
TDO
TEA
TMS
I
I/O
I/O
I
I
O
I
I
* See pin diagram (page 2) for specific pin assignment of these bus signals.
5/36
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