HD74ALVCH16500
18-bit Universal Bus Transceivers with 3-state Outputs
ADE-205-167 (Z)
Preliminary, 1st. Edition
December 1996
Description
Data flow in each direction is controlled by output enable (OEAB and
OEBA),
latch enable (LEAB and
LEBA), and clock (CLKAB and
CLKBA)
inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if
CLKAB
is held at a
high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the high to low
transition of
CLKAB.
Output enable OEAB is active high. When OEAB is high, the B port outputs are
active. When OEAB is low, the B port outputs are in the high impedance state. Data flow for B to A is
similar to that of A to B but uses
OEBA,
LEBA, and
CLKBA.
The output enables are complementary
(OEAB is active high, and
OEBA
is active low). Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
Features
•
•
•
•
•
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current
±24
mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pull-up / pulldown resistors
HD74ALVCH16500
Function Table
*3
Inputs
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↓
↓
H
L
A
X
L
H
L
H
X
X
Z
L
H
L
H
B
0
B
0
*1
*2
Output B
H : High level
L : Low level
X : Immaterial
Z : High impedance
↓
: High to low transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. Output level before the indicated steady state input conditions were established, provided that
CLKAB
was low before LEAB went low.
3. A to B data flow is show; B to A flow is similar but uses
OEBA,
LEBA, and
CLKBA.
2
HD74ALVCH16500
Pin Arrangement
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
V
CC
7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V
CC
22
A16 23
A17 24
GND 25
A18 26
OEBA
27
LEBA 28
56 GND
55
CLKAB
54 B1
53 GND
52 B2
51 B3
50 V
CC
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 V
CC
34 B16
33 B17
32 GND
31 B18
30
CLKBA
29 GND
(Top view)
3
HD74ALVCH16500
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1, 2
Symbol
V
CC
V
I
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
Output voltage
*1, 2
Input clamp current
Output clamp current
Continuous output current
V
O
I
IK
I
OK
I
O
–0.5 to V
CC
+0.5
–50
±50
±50
±100
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature
Notes:
P
T
Tstg
1
–65 to 150
W
°C
TSSOP
V
mA
mA
mA
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Unit
V
V
Except I/O ports
I/O ports
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
4
HD74ALVCH16500
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating temperature
∆t
/
∆v
Ta
0
–40
Max
3.6
V
CC
V
CC
–12
–12
–24
12
12
24
10
85
ns / V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Logic Diagram
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
1D
C1
CLK
54
B1
To seventeen other channels
5
FPGA/CPLD
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