MTD20P06HDL
Preferred Device
Power MOSFET
20 Amps, 60 Volts, Logic
Level
P−Channel DPAK
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This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low−voltage, high−speed switching applications in power supplies,
converters and PWM motor controls, and other inductive loads. The
avalanche energy capability is specified to eliminate the guesswork in
designs where inductive loads are switched, and to offer additional
safety margin against unexpected voltage transients.
•
Ultra Low R
DS(on)
, High−Cell Density, HDTMOS
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Avalanche Energy Specified
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MW)
Gate−Source Voltage
− Continuous
− Non−Repetitive (t
p
v10
ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (t
p
v10
ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
C
= 25°C
(Note 2)
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc,
I
L
= 15 Apk, L = 2.7 mH, R
G
= 25
W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
60
60
"15
"20
15
9.0
45
72
0.58
1.75
−55 to
150
300
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
1 2
20 AMPERES
60 VOLTS
R
DS(on)
= 175 mW
P−Channel
D
G
S
MARKING
DIAGRAM
4
4
Drain
YWW
20P
06HL
2
1 Drain 3
Gate
Source
= Device Code
= Year
= Work Week
Shipping
†
75 Units/Rail
2500 Tape & Reel
DPAK
DPAK
Publication Order Number:
MTD20P06HDL/D
3
DPAK
CASE 369C
(Surface Mount)
Style 2
20P06HL
Y
WW
T
J
, T
stg
E
AS
ORDERING INFORMATION
mJ
Device
MTD20P06HDL
°C/W
MTD20P06HDLT4
Package
R
qJC
R
qJA
R
qJA
T
L
1.73
100
71.4
260
°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. inch pad size.
©
Semiconductor Components Industries, LLC, 2004
1
March, 2004 − Rev. 4
MTD20P06HDL
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±15
Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance
(V
GS
= 5.0 Vdc, I
D
= 7.5 Adc)
Drain−Source On−Voltage (V
GS
= 5.0 Vdc)
(I
D
= 15 Adc)
(I
D
= 7.5 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 10 Vdc, I
D
= 7.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 48 Vdc, I
D
= 15 Adc,
V
GS
= 5.0 Vdc)
(V
DS
= 30 Vdc, I
D
= 15 Adc,
V
GS
= 5.0 Vdc,
5 0 Vdc
)
R
G
= 9.1
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 15 Adc, V
GS
= 0 Vdc)
(I
S
= 15 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 15 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
L
D
L
S
−
−
4.5
7.5
−
−
nH
nH
t
a
t
b
Q
RR
−
−
−
−
2.5
1.9
64
50
14
0.177
3.0
−
−
−
−
−
mC
ns
Vdc
−
−
−
−
−
−
−
−
19
175
41
68
20.6
3.7
7.6
8.4
38
350
82
136
29
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
850
210
66
1190
290
130
pF
V
GS(th)
1.0
−
R
DS(on)
V
DS(on)
−
−
g
FS
9.0
2.3
1.6
11
3.0
2.0
−
mhos
−
1.7
3.9
143
2.0
−
175
Vdc
mV/°C
mW
Vdc
V
(BR)DSS
60
−
I
DSS
−
−
I
GSS
−
−
−
−
1.0
10
100
nAdc
−
81.3
−
−
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
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MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
30
25
I D , DRAIN CURRENT (AMPS)
20
15
10
5V
5
0
4V
0
1
2
3
4
5
6
7
8
9
10
30
8V
I D , DRAIN CURRENT (AMPS)
25
T
J
= − 55°C
20
100°C
15
10
5
0
T
J
= 25°C
V
GS
= 10 V
9V
V
DS
≥
5 V
25°C
7V
6V
1
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.40
V
GS
= 5 V
0.275
0.250
0.225
0.200
0.175
T
J
= 25°C
0.32
0.24
T
J
= 100°C
0.16
25°C
− 55°C
0.08
V
GS
= 5 V
0.150
0.125
0.100
0
5
10
10 V
15
20
25
30
0
0
5
10
15
20
25
30
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
− 50
− 25
0
25
50
75
100
125
150
I DSS, LEAKAGE (nA)
V
GS
= 5 V
I
D
= 7.5 A
100
V
GS
= 0 V
T
J
= 125°C
10
100°C
1
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTD20P06HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
2500
C
iss
2000
C, CAPACITANCE (pF)
V
DS
= 0 V
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
1500
C
rss
1000
C
iss
500
C
rss
0
10
5
V
GS
0
V
DS
5
10
C
oss
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
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4
MTD20P06HDL
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
QT
5
4
V
DS
3
Q1
2
1
0
Q3
0
4
8
12
16
20
Q2
I
D
= 15 A
T
J
= 25°C
V
GS
50
45
40
35
30
25
20
15
10
5
0
24
1000
V
DD
= 30 V
I
D
= 15 A
V
GS
= 5.0 V
T
J
= 25°C
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t
r
t
f
t
d(off)
t
d(on)
100
t, TIME (ns)
10
1
1
10
R
G
, GATE RESISTANCE (Ohms)
100
Q
G
, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
15
I S , SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
12
9
6
3
0
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
V
SD
, SOURCE−TO−DRAIN VOLTAGE (Volts)
Figure 10. Diode Forward Voltage versus Current
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