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UPD72851GT-E1: 产品描述Serial I/O Controller, 4 Channel(s), 50MBps, CMOS, PDSO48, 9.53 MM, PLASTIC, SSOP-48; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小288KB，共48页; 制造商NEC(日电)

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UPD72851GT-E1概述

Serial I/O Controller, 4 Channel(s), 50MBps, CMOS, PDSO48, 9.53 MM, PLASTIC, SSOP-48

UPD72851GT-E1规格参数

参数名称	属性值
零件包装代码	SSOP
包装说明	SSOP,
针数	48
Reach Compliance Code	unknown
其他特性	ALSO OPERATES WITH 3.3V SUPPLY
地址总线宽度
边界扫描	YES
最大时钟频率	24.576 MHz
最大数据传输速率	50 MBps
外部数据总线宽度	8
JESD-30 代码	R-PDSO-G48
低功率模式	NO
串行 I/O 数	4
端子数量	48
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	SSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH
认证状态	Not Qualified
座面最大高度	2 mm
最大供电电压	3.6 V
最小供电电压	2.7 V
标称供电电压	3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
宽度	8 mm
uPs/uCs/外围集成电路类型	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD72851

IEEE1394a-2000 COMPLIANT 400 Mbps ONE-PORT PHY LSI

The

PD72851 is a one-port physical layer LSI that complies with the IEEE1394a-2000 specifications.

The

PD72851 supports transfers of up to 400 Mbps and consumes less power than the

PD72850B. The

PD72851 is suitable for battery systems with an IEEE1394 interface.

FEATURES

• The one-port physical layer LSI complies with IEEE1394a-2000

• Fully interoperable with IEEE1394 std 1394 Link (FireWire

, i.LINK

)

• Meets Intel

Mobile Power Guideline 2000

• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-

speed concatenation, arbitration acceleration, fly-by concatenation

• Fully compliant with OHCI requirements

• Small package: 48-pin plastic SSOP

• Super low power: 52 mA (Operating mode)

: 115

A (Suspend mode)

• Data rate: 400/200/100 Mbps

• Supports PHY pinging and remote PHY access packets

• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)

• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency

• 64-bit flexible register incorporated in PHY register

• Electrically isolated Link interface

• Supports LPS/Link-on as part of PHY/Link interface

• External filter capacitors for PLL not required

• Extended Resume signaling for compatibility with legacy DV devices

• System power management by signaling of node power class information

• Cable power monitor (CPS) is equipped

ORDERING INFORMATION

Part number

Package

48-pin plastic SSOP (9.53 mm (375))

PD72851GT-E1

PD72851GT-E2

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. S15262EJ1V0DS00 (1st edition)

Date Published January 2001 NS CP(K)

Printed in Japan

2001

PD72851

CONTENTS

1. PIN

1.1

1.2

1.3

1.4

1.5

1.6

FUNCTIONS..................................................................................................................................... 7

Cable Interface Pins ........................................................................................................................ 7

Link Interface Pins........................................................................................................................... 7

Control Pins ..................................................................................................................................... 8

IC ....................................................................................................................................................... 8

Power Supply Pins .......................................................................................................................... 8

Other Pins ........................................................................................................................................ 8

2. PHY REGISTERS..................................................................................................................................... 9

2.1 Complete Structure for PHY Registers.......................................................................................... 9

2.2 Port Status Page (Page 000)......................................................................................................... 12

2.3 Vendor ID Page (Page 001) ........................................................................................................... 13

2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 13

3. INTERNAL FUNCTION.......................................................................................................................... 14

3.1 Link Interface ................................................................................................................................. 14

3.1.1 Connection Method............................................................................................................................... 14

3.1.2 LPS (Link Power Status)....................................................................................................................... 14

3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins .................................................................................................... 14

3.1.4 SCLK..................................................................................................................................................... 14

3.1.5 LKON .................................................................................................................................................... 15

3.1.6 DIRECT................................................................................................................................................. 15

3.1.7 Isolation Barrier..................................................................................................................................... 15

3.2 Cable Interface............................................................................................................................... 17

3.2.1 Connections .......................................................................................................................................... 17

3.2.2 Cable Interface Circuit .......................................................................................................................... 18

3.2.3 CPS....................................................................................................................................................... 18

3.3 Suspend/Resume .......................................................................................................................... 18

3.3.1 Suspend/Resume On Mode.................................................................................................................. 18

3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 19

3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 19

3.4.2 PLL........................................................................................................................................................ 19

3.5 CMC ................................................................................................................................................ 19

3.6 RESETB .......................................................................................................................................... 19

3.7 RI1 ................................................................................................................................................... 19

4. PHY/LINK INTERFACE ......................................................................................................................... 20

4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface ............................................ 20

4.2 Link-on Indication.......................................................................................................................... 21

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)....................................................... 22

4.3.1 CTL0, CTL1 .......................................................................................................................................... 22

4.3.2 LREQ .................................................................................................................................................... 22

4.3.3 PHY/Link Interface Timing .................................................................................................................... 26

4.4 Acceleration Control ..................................................................................................................... 27

4.5 Transmit Status ............................................................................................................................. 28

4.6 Transmit ......................................................................................................................................... 29

Data Sheet S15262EJ1V0DS

UPD72851GT-E1相似产品对比

	UPD72851GT-E1	UPD72851GT-E2
描述	Serial I/O Controller, 4 Channel(s), 50MBps, CMOS, PDSO48, 9.53 MM, PLASTIC, SSOP-48	Serial I/O Controller, 4 Channel(s), 50MBps, CMOS, PDSO48, 9.53 MM, PLASTIC, SSOP-48
零件包装代码	SSOP	SSOP
包装说明	SSOP,	SSOP,
针数	48	48
Reach Compliance Code	unknown	unknown
其他特性	ALSO OPERATES WITH 3.3V SUPPLY	ALSO OPERATES WITH 3.3V SUPPLY
边界扫描	YES	YES
最大时钟频率	24.576 MHz	24.576 MHz
最大数据传输速率	50 MBps	50 MBps
外部数据总线宽度	8	8
JESD-30 代码	R-PDSO-G48	R-PDSO-G48
低功率模式	NO	NO
串行 I/O 数	4	4
端子数量	48	48
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	SSOP
封装形状	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
认证状态	Not Qualified	Not Qualified
座面最大高度	2 mm	2 mm
最大供电电压	3.6 V	3.6 V
最小供电电压	2.7 V	2.7 V
标称供电电压	3 V	3 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm
端子位置	DUAL	DUAL
宽度	8 mm	8 mm
uPs/uCs/外围集成电路类型	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

UPD72851GT-E1

UPD72851GT-E1概述

UPD72851GT-E1规格参数

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