DATA SHEET
BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT
µ
PB1008K
REFERENCE FREQUENCY 27.456 MHz, 2ndIF FREQUENCY 132 kHz
RF/IF FREQUENCY DOWN-CONVERTER +
PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER
DESCRIPTION
The
µ
PB1008K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion
RF block integrated Pre-Amplifier + RF/IF down-converter + PLL frequency synthesizer on 1 chip.
This IC has IQ recovery function, builds a 2-bit A/D converter in both I channels and Q channels, respectively, and
carries them in 36-pin plastic QFN package.
This IC is manufactured using our 30 GHz f
max
UHS0 (Ultra High Speed Process) silicon bipolar process.
FEATURES
• Double conversion
• Integrated RF block
• Needless to input counter data
• VCO side division
• Reference division
• Supply voltage
• Low current consumption
• Gain adjustable externally
• Power-save function
• High-density surface mountable
: f
REFin
= 27.456 MHz, f
1stIFin
= 175.164 MHz, f
2ndIFin
= 132 kHz
: Pre-Amplifier + RF/IF frequency down-converter + PLL frequency synthesizer
: The 2-bit A/D converter is unified to single chip.
: fixed division internal prescaler
:
÷102
(÷8,
÷12.75
serial prescaler)
:
÷2
: V
CC
= 2.7 to 3.3 V
: I
CC
= 18.0 mA TYP. @ V
CC
= 3.0 V
: Gain control voltage pin (control voltage up vs. gain down)
: Power-save dark current I
CC
(PD) = 10
µ
A MAX.
: 36-pin plastic QFN
APPLICATIONS
• Consumer use GPS receiver of reference frequency 27.456 MHz, 2nd IF frequency 132 kHz (for general use)
ORDERING INFORMATION
Part Number
Package
36-pin plastic QFN
Supplying Form
•
12 mm wide embossed taping
•
Pin 1 indicates pull-out direction of tape
•
Qty 2.5 kpcs/reel
µ
PB1008K-E1
Remark
To order evaluation samples, contact your nearby sales office.
Part number for sample order:
µ
PB1008K
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices
representative for availability and additional information.
Document No. PU10282EJ01V0DS (1st edition)
Date Published November 2003 CP(K)
Printed in Japan
NEC Compound Semiconductor Devices 2003
µ
PB1008K
PRODUCT LINE-UP (T
A
= +25°C, V
CC
= 3.0 V)
Type
Part Number
Functions
(Frequency unit: MHz)
Clock
Frequency
Specific
1 chip IC
V
CC
(V)
2.7 to 3.3
I
CC
(mA)
18.0
CG
(dB)
100 to
120
36-pin plastic QFN
New Device
Package
Status
µ
PB1008K
Pre-amplifier + RFdown-
converter + IQ down-converter
+ IF amplifier + 2-bit ADC +
PLL synthesizer
REF = 27.456
1stIF = 175.164/2ndIF = 0.132
On-chip 2-bit ADC
µ
PB1007K
Pre-amplifier + RF/IF down-
converter + PLL synthesizer
REF = 16.368
1stIF = 61.380/2ndIF = 4.092
2.7 to 3.3
25.0
100 to
120
36-pin plastic QFN
Available
µ
PB1005K
REF = 16.368
1stIF = 61.380/2ndIF = 4.092
36-pin plastic QFN
Available
Remark
Typical performance. Please refer to
ELECTRICAL CHARACTERISTICS
in detail.
To know the associated products, please refer to their latest data sheets.
SYSTEM APPLICATION EXAMPLE
GPS receiver RF block diagram
Basic frequency in a figure is set to f
0
= 1.023 MHz.
RF
SAW
NE696M01
NF = 1.2 dB
G =17 dB
IQ Demod
LNA
1st Mixer
L/C filter
AGC
2-bit
ADC
ISign
IMag
1 400.256 MHz TANK
/2
/4
2-bit
ADC
QSign
QMag
Loop
Filter
/6
/7
/8
/2
/2
PLL Frequency
Counters
Regulator Circuitry
REFin
27.456 MHz
Reference
Clock
Caution This diagram schematically shows only the
µ
PB1008K’s internal functions on the system.
This diagram does not present the actual application circuits.
2
Data Sheet PU10282EJ01V0DS
BASEBAND IC
µ
PB1008K
PIN CONNECTION AND INTERNAL BLOCK DIAGRAM
2ndIFout-lb
DCoffsetIb
2ndIFout-I
DCoffsetI
27
V
CCanalog
28
V
AGC
29
IF-in1 30
IF-in2 31
GND
analog
32
Mixout2 33
Mixout1 34
V
REF
35
LNAbias 36
1
GND LNA
26
25
24
23
22
21
20
19
18 GNDbb
V
th
2-bit
ADC
2-bit
ADC
Qmag
Qsign
V
CCbb
Imag
Isign
V
th
17 DCoffsetQb
16 DCoffsetQ
15 2ndIFout-Qb
/4
14 2ndIFout-Q
13 PD1
/2
/2
/6/7
PD
/8
/2
12 IC Cntl
11 GNDdig
10 REFin
2
LNAin
3
V
CCrf
4
GND
LO
5
1stLO-OSC1
6
1stLO-OSC2
7
V
CCLO
8
PD
out
9
V
CCdig
Data Sheet PU10282EJ01V0DS
3
µ
PB1008K
PIN EXPLANATION
Pin
No.
1
GND LNA
Ground pin of LNA.
3
36
2
V
CC
Pin Name
Function and Application
Internal Equivalent Circuit
2
LNAin
Input pin of low noise amplifier.
It is a single-ended open
collector design. Capacitive
coupling is required; external
matching will improve gain or
NF.
Regulator
Bias
6.5 kΩ
1
3
V
CCrf
Supply voltage pin of LNA, RF
mixer and VCO voltage
regulator.
410
Ω
7
4
GND
LO
Ground pin of 1stLO oscillator
circuit and RF Mixer.
6
3
400
Ω
1.8 pF
1.8 pF
400
Ω
5
V
CC
4.4 kΩ
Bias
5
1stLO-OSC1
Pin 5 & 6 are base pins of the
differential amplifier for 1stLO
oscillator. These pins requre an
LC (varacator) tank circuit to
4.4 kΩ
6
1stLO-OSC2
oscilate at around 1 400 MHz.
Regulator
idc = 941
µ
7
V
CCLO
Supply voltage pin of oscillator
circuit for 1stLO oscillator and
RF mixer.
4
8
PD
out
This is a cirrent mode charge
pump output. For connection to
a passive RC loop filter for
driving external varactor diode
FROM PFD
Source
PFD
9
of 1stLO oscillator.
Source
Control
ESD
8
9
V
CCdig
Supply voltage pin of digital
portion of the chip.
PFD
Sink
Sink
Control
ESD
11
4
Data Sheet PU10282EJ01V0DS
µ
PB1008K
Pin
No.
10
REFin
Input pin of reference frequency
buffer. This pin should be
equipped with external 27 MHz
oscillator (e.g. TCXO).
ESD
10
20 kΩ
20 kΩ
idc = 9.7
µ
9
Pin Name
Function and Application
Internal Equivalent Circuit
11
GNDdig
Ground pin of digital portion of
the chip.
ESD
500
Ω
500
Ω
30 kΩ
50 kΩ
idc = 22
µ
5.4 pF
11
12
IQ cntl
The voltage on this pin controls
the Q channel IF amplifier gain
control of
±2
dB can be
achieved for 0 to 3 V.
Leave open-circuited if not
used.
12
idc = 23.5
µ
200 kΩ
28
idc = 23.5
µ
I
REF
12 kΩ
CCCS
7.1 kΩ
7.1 kΩ
7.1 kΩ
7.1 kΩ
32
13
PD1
Standby mode control.
Low = whole chip OFF & High =
Whole chip ON.
V
CC
ESD
13
28 kΩ
ESD
11
Data Sheet PU10282EJ01V0DS
5
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