FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
April 2007
FMS6501
12 Input / 9 Output Video Switch Matrix with Input Clamp,
Input Bias Circuitry, and Output Drivers
Features
■
12 x 9 Crosspoint Matrix
■
Supports SD, PS, and HD 1080i/1080p Video
■
Input Clamp / Bias Circuitry
■
AC or DC-Coupled Inputs
■
AC or DC-Coupled Outputs
■
Dual-Load (75Ω) Output Drivers with High-Impedance
■
■
■
■
■
Description
The FMS6501 switch matrix provides flexible options for
today’s video applications. The 12 inputs that can be
routed to any of nine outputs. Each input can be routed
to one or more outputs, but only one input may be routed
to any one output. The input to output routing is con-
trolled via an I
2
C™-compatible digital interface.
Each input supports an integrated clamp option to set the
output sync tip level of video with sync to ~300mV. Alter-
natively, the input may be internally biased to center sig-
nals without sync (Chroma, Pb, Pr) at ~1.25V. These DC
output levels are for the 6dB gain setting. Higher gain
settings increase the DC output levels accordingly. The
input clamp / bias mode is selected via I
2
C.
Unused outputs may be powered down to reduce power
dissipation.
Disable
One-to-One or One-to-Many Input to Output Switching
Programmable Gain: +6, +7, +8, or +9dB
I
2
C
TM
Compatible Digital Interface, Standard Mode
3.3V or 5V Single-Supply Operation
Lead-Free SSOP-28 Package
Applications
■
Cable and Satellite Set-Top Boxes
■
TV and HDTV Sets
■
A/V Switchers
■
Personal Video Recorders (PVR)
■
Security / Surveillance
■
Video Distribution
■
Automotive (In-Cabin Entertainment)
Ordering Information
Part Number
FMS6501MSA28
FMS6501MSA28X
Pb-Free
Yes
Yes
Temperature Range
-40°C to 85°C
-40°C to 85°C
Package
SSOP-28
SSOP-28
Container
Rail
Reel
Quantity
47
2000
© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
www.fairchildsemi.com
FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Block Diagram
IN1
C/B
IN2
C/B
IN12
C/B
SDA
SCL
ADDR
VCC (2)
GND (2)
OUT1
OUT2
OUT9
Programmable
Enable/Disable
Programmable Gain
6, 7, 8, or 9dB
Figure 1. FMS6501 Block Diagram
© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
www.fairchildsemi.com
2
FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Pin Configuration
Pin Assignments
Pin#
Name
IN1
IN2
IN3
IN4
IN5
IN6
VCC
GND
IN7
IN8
IN9
IN10
IN11
IN12
ADDR
SCL
SDA
OUT9
OUT8
OUT7
GNDO
VCCO
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Description
Input, channel 1
Input, channel 2
Input, channel 3
Input, channel 4
Input, channel 5
Input, channel 6
Positive power supply
Must be tied to ground
Input, channel 7
Input, channel 8
Input, channel 9
Input, channel 10
Input, channel 11
Input, channel 12
Selects I
2
C address. “0” = 0x06
(0000 0110), ‘1” = 0x86 (1000 0110)
Serial clock for I
2
C port
Serial data for I
2
C port
Output, channel 9
Output, channel 8
Output, channel 7
Must be tied to ground
Positive power supply for output drivers
Output, channel 6
Output, channel 5
Output, channel 4
Output, channel 3
Output, channel 2
Output, channel 1
IN1
IN2
IN3
IN4
IN5
IN6
VCC
GND
IN7
IN8
IN9
IN10
IN11
IN12
1
2
3
4
5
6
28
27
26
25
OUT1
1
OUT2
OUT3
OUT4
OUT5
OUT6
VCCO
GNDO
OUT7
OUT8
2
3
4
5
6
7
8
9
10
11
12
FAIRCHILD
FMS6501
24
23
28L SSOP
7
8
9
10
11
12
13
14
22
21
20
19
18
17
16
15
OUT9
SDA
SCL
ADDR
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Figure 2. Pin Configuration
© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
www.fairchildsemi.com
3
FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Parameter
DC Supply Voltage
Analog and Digital I/O
Output Current Any One Channel, Do Not Exceed
Min.
-0.3
-0.3
Max.
6.0
V
cc
+ 0.3
40
Unit
V
V
mA
Reliability Information
Symbol
T
J
T
STG
T
L
Θ
JA
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Thermal Resistance, JEDEC Standard Multilayer Test Board, Still Air
50
-65
Parameter
Min.
Typ.
Max.
150
150
300
Unit
°C
°C
°C
°C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
CC
Supply Voltage Range
Parameter
Operating Temperature Range
Min.
-40
3.135
Typ.
5.000
Max.
85
5.250
Unit
°C
V
Electrostatic Discharge Protection
Symbol
HBM
CDM
Human Body Model
Charged Device Model
Parameter
Value
5
2
Unit
kV
kV
© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
www.fairchildsemi.com
4
FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Digital Interface
The I
2
C-compatible interface is used to program output
enables, input to output routing, input clamp / bias, and
output gain. The I
2
C address of the FMS6501 is 0x06
(0000 0110) with the ability to offset it to 0x86 (1000
0110) by tying the ADDR pin high.
Both data and address data, of eight bits each, are writ-
ten to the I
2
C address to access all the control functions.
There are separate internal addresses for each output.
Each output’s address includes bits to select an input
channel, adjust the output gain, and enable or disable
the output amplifier. More than one output can select the
same input channel for one-to-many routing. When the
outputs are disabled, they are placed in a high-imped-
ance state. This allows multiple FMS6501 devices to be
paralleled to create a larger switch matrix. Typical output
power-up time is less than 500ns.
The clamp / bias control bits are written to their own
internal address, since they should always remain the
same regardless of signal routing. They are set based on
the input signal connected to the FMS6501.
All undefined addresses may be written without effect.
Output Control Register Contents and Defaults
Control Name
Enable
Gain
Inx
Width
1 bit
2 bits
5 bits
Type
Write
Write
Write
Default
0
0
0
Bit(s)
7
6:5
4:0
Description
Channel Enable: 1=Enable, 0=Power Down
(1)
Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB
Input selected to drive this output: 00000=OFF
(2)
,
00001=IN1, 00010=IN2... 01100=IN12
Notes:
1. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled. Power
down also de-selects any input routed to the specified output.
2. When all inputs are OFF, the amplifier input is tied to approximately 150mV and the output goes to approximately
300mV with the 6dB gain setting.
Output Control Register MAP
Register Register
Name
Address
Bit 7
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Bit 6
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Bit5
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Bit4
(1)
IN4
IN4
IN4
IN4
IN4
IN4
IN4
IN4
IN4
Bit3
IN3
IN3
IN3
IN3
IN3
IN3
IN3
IN3
IN3
Bit2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
Bit1
IN1
IN1
IN1
IN1
IN1
IN1
IN1
IN1
IN1
Bit0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
Notes:
1. IN4 is provided for forward compatibility and should always be written as ‘0’ in the FMS6501.
Clamp Control Register Contents and Defaults
Control Name
Clmp
Width
1 bit
Type
Write
Default
0
Bit(s)
7:0
Description
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Clamp Control Register Map
Register Name
CLAMP1
CLAMP2
Register
Address
0x1D
0x1E
Bit 7
Clmp8
Resv’d
Bit 6
Clmp7
Resv’d
Bit5
Clmp6
Resv’d
Bit4
Clmp5
Resv’d
Bit3
Clmp4
Clmp12
Bit2
Clmp3
Clmp11
Bit1
Clmp2
Clmp10
Bit0
Clmp1
Clmp9
© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
www.fairchildsemi.com
5
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