FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
April 2008
FIN12AC
Low-Voltage 12-Bit Bi-Directional
Serializer/Deserializer with Multiple Frequency Ranges
Features
■
Low power consumption
■
Fairchild proprietary low-power CTL™ interface
■
LVCMOS parallel I/O interface:
Description
The FIN12AC is a 12-bit serializer / deserializer capable
of running a parallel frequency range between 5MHz
and 40MHz, selected by the S1 and S2 control signals.
The bi-directional data flow is controlled through use of a
direction (DIRI) control pin. The devices can be config-
ured to operate in a unidirectional mode only by hardwir-
ing the DIRI pin. An internal Phase-Locked Loop (PLL)
generates the required bit clock frequency for transfer
across the serial link. Options exist for dual or single PLL
operation, dependent upon system operational parame-
ters. The device has been designed for low power opera-
tion and utilizes Fairchild proprietary low-power control
Current Transistor Logic (CTL™) interface. The device
also supports an ultra low power power-down mode for
conserving power in battery-operated applications.
■
■
■
■
■
■
■
■
■
■
– 2mA source / sink current
– Over-voltage tolerant control signals
Parallel I/O power supply (V
DDP
) range between
1.65V and 3.6V
Analog power supply range of 2.5V to 3.3V
Multi-mode operation allows for a single device to
operate as Serializer or Deserializer
Internal PLL with no external components
Standby power-down mode support
Small footprint packaging:
– 32-terminal MLP and 42-ball BGA
Built-in differential termination
Supports external CKREF frequencies; 5MHz to 40MHz
Serialized data rate up to 560Mb/s
Voltage translation from 1.65V to 3.6V
Applications
■
Microcontroller or pixel interfaces
■
Image sensors
■
Small displays: LCD, cell phone, digital camera,
portable gaming, printer, PDA, video camera,
automotive
Ordering Information
Part Number
FIN12ACGFX
FIN12ACMLX
Operating
Temperature Range
-30 to +70°C
-30 to +70°C
Package
42-Ball Ultra Small Scale Ball Grid Array
(USS-BGA), JEDEC MO-195, 3.5mm Wide
32-Terminal Molded Leadless Package
(MLP), Quad, JEDEC MO-220, 5mm Square
Packing
Method
Tape and Reel
Tape and Reel
Pb-free package per JEDEC J-STD-020B.
µSerDes
™
is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Functional Block Diagram
CKREF
STROBE
Register
DP[21:22]
PLL
0
cksint
I
Serializer
Control
Serializer
+
-
DSO+/DSI-
DSO-/DSI+
+
-
CKS0+
CKS0-
DP[1:20]
oe
Register
Deserializer
Deserializer
Control
cksint
+
-
+
-
100 Gated
Termination
CKSI+
CKSI-
100
Termination
DP[23:24]
Register
CKP
WORD CK
Generator
Control Logic
S1
S2
DIRI
Power Down
Control
Freq
Control
Direction
Control
oe
DIRO
Figure 1. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
2
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Terminal Descriptions
Pin Name
DP[1:12]
CKREF
STROBE
CKP
I/O Type
I/O
IN
IN
OUT
Number of
Terminals
12
1
1
1
Description of Signals
LVCMOS parallel I/O, Direction controlled by DIRI pin
LVCMOS clock input and PLL reference
LVCMOS strobe signal for latching data into the serializer
LVCMOS word clock output. This signal is the regenerated STROBE
signal
CTL differential serial I/O data signals
(1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CTL differential deserializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
Used to define frequency range for the RefClock, CKREF.
Used to define PLL multiplication mode.
PLLX_SEL = 0 multiplication factor 7-1/3x
PLLX_SEL = 1 multiplication factor 7x
LVCMOS control input. Used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
LVCMOS output, inversion of DIRI
Power supply for parallel I/O and translation circuitry
Power supply for core and serial I/O
Power supply for analog PLL circuitry
Use bottom ground plane for ground signals
DSO+ / DSI-
DSO- / DSI+
DIFF-I/O
2
CKSI+ / CKSI-
DIFF-IN
2
CKSO+ / CKSO-
DIFF-OUT
2
S1
S2
PLLx_SEL
IN
IN
IN
1
1
1
DIRI
DIRO
V
DDP
V
DDS
V
DDA
GND
IN
OUT
Supply
Supply
Supply
Supply
1
1
1
1
1
0
Note:
1
The DSO/DSI serial port pins have been arranged such that if one device is rotated 180° with respect to the other
device, the serial connections properly aligns without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross
.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
3
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Pin Assignments
Terminal Assignments for MLP
27
STROBE
26
CKREF
32
DP[3]
31
DP[2]
30
DP[1]
25
DIRO
29
N/C
28
N/C
Pin Assignments for BGA
1
24
CKSO+
23
CKSO-
22
DSO+/DSI-
21
DSO-/DSI+
20
CKSI-
19
CKSI+
18
DIRI
17
V
DDS
2
3
4
5
6
DP[4]
DP[5]
DP[6]
V
DDP
CKP
DP[7]
DP[8]
DP[9]
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
(Top View)
10
11
12
13
14
15
BGA Pin Assignments
1
A
B
C
D
E
F
G
DP4
DP6
CKP
N/C
DP8
DP10
DP12
2
DP2
DP5
N/C
DP7
DP9
DP11
N/C
3
N/C
DP1
DP3
V
DDP
GND
N/C
N/C
4
N/C
N/C
N/C
GND
V
DDS
V
DDA
PLLx_SEL
5
N/C
STROBE
CKSO+
DSO-/DSI+
CKSI+
N/C
S2
6
CKREF
DIRO
CKSO-
DSO+/DSI-
CKSI-
DIRI
S1
N/C = No Connect
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
DP[10]
DP[11]
DP[12]
N/C
PLLx_SEL
S2
S1
V
DDA
(Top View)
Figure 2. Terminal and Pin Assignments
16
9
www.fairchildsemi.com
4
FIN12AC — Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
Control Logic Circuitry
The FIN12AC can be used as a 12-bit serializer or a 12-
bit deserializer. Terminals S1 and S2 must be set to
accommodate the clock reference input frequency range
of the serializer. Table 1 shows the terminal program-
ming of these options based on the S1 and S2 control
terminals. When DIRI is asserted LOW, the device is
configured as a deserializer. When the DIRI terminal is
asserted HIGH, the device is configured as a serializer.
Changing the state on the DIRI signal reverses the direc-
tion of the I/O signals and generates the opposite state
signal on DIRO. For unidirectional operation, the DIRI
terminal should be hardwired to the HIGH or LOW state
and the DIRO terminal should be left floating. For bi-
directional operation, the DIRI of the master device is
driven by the system and the DIRO signal of the master
is used to drive the DIRI of the slave device.
Turn-Around Functionality
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGH-
impedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned into a deseri-
alizer and the values are overwritten.
Power-Down Mode
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differ-
ential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS out-
puts are placed into a HIGH-impedance state, LVCMOS
inputs are driven to a valid level internally, and all internal
circuitry are reset. The loss of CKREF state is also
enabled to ensure that the PLL only powers up if there is
a valid CKREF signal.
In a typical application mode, signals of the device do not
change other than between the desired frequency range
and the power-down mode. This allows for system-level
power-down functionality to be implemented via a single
wire for a SerDes pair. The S1 and S2 selection signals
that have their operating mode driven to a “logic 0”
should be hardwired to GND. The S1 and S2 signals that
have their operating mode driven to a “logic 1” should be
connected to a system-level power-down signal.
PLL Multiplier
The multiply select pin PLLx_SEL determines whether
the PLL multiplication factor is 7 times the CKREF fre-
quency or 7-1/3 times the CKREF frequency. Overclock-
ing the PLL increases the range of spread spectrum on
the CKREF input clock that can be tolerated.
Both of the PLL multiplier modes can work with a non-
spread spectrum clock. When operating with the stan-
dard 7x multiplier and operating in a CKREF = STROBE
mode, the serialized word is 14 data bits long. Each
deserializer output period has the same period of the
STROBE signal.
In the overclocking mode, the average deserializer
period is the same as the STROBE signal. The individual
periods vary between 14 and 16 data bits long. The pat-
tern repeats every three cycles with two 14-bit cycles,
followed by a third 16-bit cycle. The last two bits in the
16-bit cycle are zero. The deserializer output clock
period has the same variation as the serializer outputs.
Table 1. Control Logic Circuitry
Mode
Number
0
1
PLLx_SEL
X
1
0
X
1
S2
0
0
0
0
1
1
1
1
1
1
S1
0
1
1
1
0
0
0
1
1
1
DIRI
X
1
1
0
1
1
0
1
1
0
Power-Down Mode
Description
12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 4.7MHz to 13.3MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF
12-Bit Deserializer
2
0
X
1
3
0
X
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.2
www.fairchildsemi.com
5
下载中心专版
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
