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µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
May 2008
FIN212AC
12-Bit Serializer Deserializer with Multiple Frequency Ranges
Features
Low Power Consumption
Low Power, Proprietary, CTL™ I/O Serial Interface
Wide PLL Input Frequency Range
Wide Parallel Supply Voltage Range: 1.65 to 3.6V
Low Power Core Operation: V
DDS/A
=2.5 to 3.6V
Built-in LV-CMOS Voltage Translation Capability
with no External Components
Adjustable Parallel Edge Rate
Operates as Serializer or Deserializer
Standby Power-Down Mode Support
Built-in Differential Termination
Description
The FIN212AC µSerDes™ is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 12-bit data path to
four wires. The device can be configured as a serializer
or deserializer through the DIRI pin, minimizing
component types in the system. For camera
applications, an additional master clock can be passed
in the opposite direction of data flow.
The device utilizes Fairchild’s proprietary ultra-low
power, low-EMI technology. LV-CMOS parallel output
buffers have been implemented with slew rate control to
adjust for capacitive loading and to minimize EMI. The
device also supports an ultra-low power-down mode for
conserving power in battery-operated applications.
The device is available in a 5x5mm MLP package to
attach directly to a flex circuit, or in two choices of BGA,
where space constraints are a concern.
Applications
8-Bit LCD Displays for Cell Phones
8/10-Bit Cell Phone Camera Interface
8-Bit LCD Displays for Printers
Related Application Notes
AN-5058 µSerDes™ Family Frequently Asked
Questions
AN-5061 µSerDes™ Layout Guidelines
Ordering Information
Order Number
FIN212ACMLX
FIN212ACGFX
FIN212ACBFX
Operating
Temperature
Range
-30 to 70°C
-30 to 70°C
-30 to 70°C
Package Description
32-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 5mm Square
42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch
36-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
2.5mm Square, 0.4mm Ball Pitch (Preliminary)
Packing
Method
Tape & Reel
Tape & Reel
Tape & Reel
All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green.
For Fairchild’s definition of “green” please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.6
www.fairchildsemi.com
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pin Definitions
Pin
DP[1:12]
CKREF
STROBE
CKP
DSO+(DSI-)
DSO-(DSI+)
(1)
I/O type
CMOS-I/O
CMOS-IN
CMOS-IN
CMOS-
OUT
DIFF-I/O
DIFF-IN
DIFF-OUT
CMOS-IN
CMOS-IN
CMOS-IN
CMOS_IN
CMOS_IN
IN
OUT
Supply
Supply
Supply
Supply
# of
Pins
12
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
0
Description of Signals
LV-CMOS Parallel I/O. Direction controlled by DIRI pin.
LV-CMOS clock input and PLL reference.
LV-CMOS strobe input for latching data into the serializer.
LV-CMOS word clock output.
CTL Differential serial I/O data signals.
DS(I)+: Positive signal of DS(I) pair; DS(I)-: Negative signal of DS(I) pair.
CTL Differential deserializer input bit clock.
CKSI+: Positive signal of CKSI pair; CKSI-: Negative signal of CKSI pair.
CTL Differential serializer output bit clock.
CKSO+: Positive signal of CKSO pair;
CKSO-: Negative signal of CKSO pair.
DIRI=1: signals are used to define frequency range for the PLL. DIRI=0:
Signals are used to define the edge rate of the deserializer parallel I/Os.
DIRI=1: PLL0 signal is used to divide or adjust the serial frequency.
DIRI=0: PWS0 signal is used to set the width of the CKP output pulse.
DIRI=1: PLL1 Signal is used to divide the serial frequency.
DIRI=0: PWS1 pin controls the output pulse width.
DIRI=1: TEST=0, Normal Operation. DIRI=0: Termination enable
functionality for deserializer. XTRM=0 Internal termination. XTRM=1
External termination required. Ground this pin for serializer.
Adjusts CTL drive for serializer. Ground this pin for deserializer.
LV-CMOS Control Input. Used to control direction of data flow: DIRI= “1”
Serializer, DIRI=“0” Deserializer
LV-CMOS Output. Inversion of DIRI in normal operation mode.
Power supply for parallel I/O and translation circuitry.
Power supply for core and serial I/O.
Power supply for analog PLL circuitry.
Ground center pad, ground D4, E3 and NCs for 42-ball BGA. Ground B5,
C2, C4 for 36-ball BGA.
(2)
CKSI+, CKSI-
CKSO+,
CKSO-
S0, S1
PLL0(PWS0)
PLL1(PWS1)
TEST / (XTRM)
CTL_ADJ
(GND)
DIRI
/DIRO
VDDP
VDDS
VDDA
GND
Notes:
1. () Indicate deserializer functionality when DIRI=0.
2. The DS serial port pins are arranged such that when one device is rotated 180 degrees from the other device,
the serial connections properly align without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
3. All unused LV-CMOS input signals should be connected to GND or VDDP. Signals can be connected directly to
the rail or through a resistor.
4. All unused LV-CMOS output signals should be allowed to float.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.6
www.fairchildsemi.com
2
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pin Configurations
DP[3]
DP[2]
DP[1]
(XTRM)
CTL_ADJ
STROBE
CKREF
/DIRO
DP[4]
DP[5]
DP[6]
VDDP
CKP
DP[7]
DP[8]
DP[9]
1
2
3
4
5
6
7
8
DP[10]
DP[11]
DP[12]
PLL1(PWS1)
PLL0(PWS0)
S1
S0
VDDA
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CKSO+
CKSO-
DSO+/DSI-
DSO-/DSI+
CKSI-
CKSI+
DIRI
VDDS
Figure 1.
Pin Assignments for 32-Pin MLP (5x5mm, .5mm Pitch, Top View)
1
A
B
C
D
E
F
G
2
3
4
5
6
A
B
C
D
E
F
G
1
DP4
DP6
CKP
N/C
DP8
DP10
DP12
2
DP2
DP5
N/C
DP7
DP9
DP11
n/c
3
XTRM
DP1
DP3
VDDP
GND
n/c
4
CTL_ADJ
n/c
n/c
GND
VDDS
VDDA
5
n/c
STROBE
CKSO+
DSO-/DSI+
CKSI+
n/c
S1
6
CKREF
/DIRO
CKSO-
DS0+/DSI-
CKSI-
DIRI
S0
PLL1(PWS1) PLL0(PWS0)
Figure 2.
(
1
A
B
C
D
E
F
2
p
3
)
4
Pin Assignments for 42 BGA (3.5x4.5mm, .5mm Pitch, Top View)
5
6
A
B
C
D
E
F
1
DP4
DP6
CKP
DP7
DP9
DP11
2
DP2
DP5
GND
DP8
DP10
DP12
3
DP1
DP3
VDDP
GND
PLL1(PWS1)
/
PLL0(PWS0)
4
(XTRM)
CTL_ADJ
GND
VDDS
S0
S1
5
STROBE
GND
CKSO+
DSO-/DSI+
CKSI+
VDDA
6
CKREF
/DIRO
CKSO-
DS0+/DSI-
CKSI-
DIRI
Figure 3.
Pin Assignments for 36 BGA (2.5x2.5mm, .4mm Pitch) Preliminary
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.6
www.fairchildsemi.com
3
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Control Logic Circuitry
Mode
PLL0
PLL1 S1 S0
0
X
X
0
0
1
1
0
0
1
1
0
0
0
1
1
X
X
0
1
2
1
0
1
0
2
0
0
1
0
2
X
X
1
0
3
1
0
1
1
3
0
0
1
1
3
X
X
1
1
Table 1. Control Logic Circuitry
DIRI
X
1
1
0
1
1
0
1
1
0
Description
Power-Down Mode
12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF
12-Bit Serializer, Over-0Clocked PLL, 4.7MHz to 13.3MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF
12-Bit Deserializer
No-Divide mode should be used for standard 8-bit pixel
interface where the STROBE and CKREF frequencies
are identical.
Divide-by-2 and Divide-by-3 modes are useful in
microcontroller interfaces where the CKREF frequency is
significantly higher than the required STROBE frequency.
DIRI=1
PLL1
PLL0
0
0
1
0
1
0
Serializer Frequency
Multiplier
7.3x
7x
3.5x
Over-clocking
No Divide
Divide by 2
Divide by 3
[DIRI] Direction Logic:
The FIN212 can be configured
as a 12-bit serializer or deserializer based on the state
of the DIRI signal. When DIRI is 1, the device is a
serializer. When DIRI is 0, the device is a deserializer.
The /DIRO signal is an inversion of the DIRI signal. The
/DIRO signal of the master can be used to drive the
DIRI signal of the slave in applications where the
interface needs to be turned around.
[S0, S1] Mode Select:
The mode select signals, S1
and S0, are used for different purposes when the device
is a serializer or a deserializer. For the serializer, the
pins need to be set to the correct value of the input
CKREF Frequency range.
For the deserializer the signals are used to select an
edge rate value. The fastest edge rates correspond to
the highest frequency mode. This relationship is
maintained for all modes.
Mode #
0
1
2
DIRI=0
S1
0
0
1
S0
0
1
0
Frequency
Range
Power-Down
FAST
SLOW
MEDIUM
1
1
2.3x
Table 3. Frequency Multipliers
Internal STROBE Filter:
When the PLL starts, the
STROBE signal is internally held off until the PLL is
locked. This prevents any spurious data from being
passed through the device.
[PWS0, PWS1] Pulse Width Adjust Circuitry:
The
word clock strobe output (CKP) pulse width can be
adjusted through the PWS0 and PWS1 signals. The
signals can be used to lengthen the width of the LOW
pulse or invert the pulse in RGB applications with a 50%
duty cycle.
DIRI=0
PWS1
PWS0
0
0
1
1
0
1
0
1
Low Time
(Bits)
No Divide
7
7
13
17
Polarity (CKP
Read Edge)
LH
HL
LH
LH
3
1
1
Table 2. Deserializer Edge Rates
[PLL0, PLL1] PLL Frequency Select Signals:
The
PLL1 and PLL0 signals provide additional flexibility in
generating the serial clock frequency. The PLLn signals
only function when the device is a serializer (DIRI=1).
When the device is a slave, these pins are used for
pulse width adjustment.
Over-clocking mode is used when the input reference
clock has been implemented with significant spread
spectrum. Over-clocking allows the serializer to tolerate
a large amount of CKREF frequency spread.
Table 4. Pulse Width Adjust Circuitry at Serial
CLK Period
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.6
www.fairchildsemi.com
4
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Power-Down Functionality:
When both S1 and S0
signals are 0, regardless of the state of the DIRI
signal, the FIN212AC resets and powers down. The
power-down mode shuts down all internal analog
circuitry, disables the serial input and output of the
device, and resets all internal digital logic. Table 5
indicates the state of the output buffers in Power-
Down mode.
Signal Pins
DP[10:1]
DP[12:11]
CKP
STROBE
CKREF
DIRI=1
Inputs Disabled
Inputs Disabled
HIGH
Input Disabled
Input Disabled
DIRI=0
Outputs HIGH-Z
Outputs HIGH-Z
Outputs HIGH-Z
Input Disabled
Input Disabled
1
[CTL_ADJ] CTL Drive Adjustment:
The drive
characteristics of the CTL I/O can be adjusted
through the CTL_ADJ pin. Standard-level CTL drive is
provided when the CTL_ADJ pin is zero. High- level
drive is provided when CTL_ADJ pin is HIGH. High-
drive should be used in noisy environments or when
driving cables longer than 20cm. When in high-drive
mode, CTL drive increases by approximately by 50%.
CTL_ADJ
0
Description
Standard CTL Drive
1
High CTL Drive
Table 6. CTL_ADJ Functionality
[(/XTRM]] Test / XTRM Mode Functionality:
For the
deserializer, the (XTRM) signal can be used to enable
or disable the internal termination resistor on the CKS
and DS signals of the deserializer. When the internal
termination is disabled, an external termination resistor
is required for the CTL I/O to operate properly.
(XTRM)
0
1
DIRI=0 (/XTRM)
Internal Termination
External Termination
/DIRO
0
Table 5. Output States
When an input is disabled, it does not draw current,
regardless of the state or level of the input signal.
All of the LV-CMOS inputs must remain driven during
power-down to ensure a low-power state
Turn-Around Functionality:
The device passes and
inverts the DIRI signal asynchronously to the /DIRO
signal. Care must be taken by the system designer to
ensure that no contention occurs between the
deserializer outputs and the other devices on this port.
Optimally the peripheral device driving the serializer
should be put into a HIGH-impedance state prior to the
DIRI signal being asserted. When a device with
dedicated data outputs turns from a deserializer to a
serializer, the dedicated outputs remain at the last
logical value asserted. This value only changes if the
device is once again turned around into a deserializer
and the values are overwritten.
Strobe Pass-Through Mode:
For some applications,
it is desirable to pass a word clock across a
differential signal pair in the opposite direction of
serialization. The FIN212 supports this mode of
operation. The following describes how to enable this
functionality for an images sensor
(see Figure 5).
Deserializer Configuration (DIRI=0)
1.
2.
1.
Connect CKREF(BGA pin A6) to GROUND
Connect master clock to STROBE (BGA pin B5)
CKSI passes master clock to CKP output (BGA
pin C1)
Table 7. (/XTRM) Functionality
Serializer Configuration (DIRI=1)
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.6
www.fairchildsemi.com
5
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