Freescale Semiconductor, Inc.
MMC2080/2075/D
Rev. 0, 10/1999
Semiconductor Products Sector
MMC2080/2075
Freescale Semiconductor, Inc...
Advance Information
MMC2080/2075 Integrated Processor with
Roaming FLEX™ Decoder
Part 1 Introduction
The MMC2080/2075 is designed to provide the messaging and paging marketplace with a powerful and
flexible solution to carry communications design into the next millennium. The MMC2080 integrates two
of Motorola’s most successful product families, M•CORE™ and the Roaming FLEX™ alphanumeric
decoders, a combination that will set a new standard in the communications industry. Except for the FLEX
decoder, the MMC2075 offers all features of the MMC2080.
Both the The MMC2080/2075 are members of the low-power, high-performance M•CORE family of 32-bit
microcontroller units (MCUs). The M•CORE is a streamlined execution engine that provides many of the
performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining
performance, speed, and cost efficiency in a compact, low-power design, the M•CORE microRISC
architecture is a natural solution for applications where battery life and systems cost are critical design goals.
Given that a total system’s components and processor core determine its power consumption, the instruction
set architecture (ISA) for the M•CORE is designed to optimize the trade-off between performance and total
power consumption. The result is system-wide reduction of total energy consumption with maintenance of
acceptable performance levels. Memory power consumption (both on-chip and external) is a major factor in
system energy consumption. By adopting 16-bit instruction encoding, and thus significantly decreasing the
memory bandwidth needed for a high rate of instruction execution, the MMC2080/2075 minimizes the
overhead of memory system energy consumption.
The MMC2080/2075 also reduces power consumption by coupling a fully static design with dynamic power
management and low-voltage operation. Versatile power management is achieved through automatic power
downs of any internal functional blocks not needed on a clock-by-clock basis. Power conservation modes
are also provided for absolute power conservation.
A table of contents for this document appears on the following page. Figure 1 on page 3 and Figure 2 on
page 4 provide simplified block diagrams of the MMC2080/2075.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Motorola, Inc., 1999. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Part 1
1.1
1.2
1.3
1.4
1.5
1.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conventions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Roaming FLEX Protocol and the MMC2080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
5
6
8
8
8
8
Part 2 Signal and Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
MMC2080/2075 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Tables of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Part 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1
General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Part 4
4.1
4.2
4.3
Pin-out and Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
BGA Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PGA Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ordering Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Freescale Semiconductor, Inc...
Part 5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
Heat Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
MMC2080/2075 Technical Data
For More Information On This Product,
Preliminary
Go to: www.freescale.com
Freescale Semiconductor, Inc.
I/O
JTAG
POR
DE
TMS
TCK
TDI
TDO
TRST
XTAL
EXTAL
PLL
SIM
OnCE
CPU
SCI
OSC
(MPIO)
INTC
Timer1
CXFC
RESET
RSTOUT
UCLK
MPC7/URXD
MPC6/UTXD
MPC5/UCTS
MPC4/URTS
MPC3/TIC1
MPC2/TOC1
MPC1/TIC0
MPC0/TOC0
MPIO
SPI1-FSC
MPE4/LOCK
MPE3/MOSI
MPE2/MISO
MPE1/SS
MPE0/SCLK
MPB[7:4]/ROW[3:0]
MPB[3:0]/COL[3:0]
MPA[5:0]
CNFG
FLEX
Melody
BGNT
BREQ
MLDY
Arbiter
SPI0
MMC2080 Only
JTAG
I/O
Freescale Semiconductor, Inc...
MPD[7:0]/D[15:8]
Timer0
96K ROM
D[7:0]
A[21:0]
EB[1:0]
BW8
WE
OE
TA
ABORT
BUSCLK
IRQ
SEL[2:0], SEL3
XBOOT
Peripheral Bus
System Bus
6K RAM
External
Bus
Bridge
APB
Keypad
LOBAT
EXTS[1:0]
CLKOUT
SYMCLK
S[7:1]
S0/IFIN
Figure 1. MMC2080/2075 144 Block Diagram (144-Pin Package)
Introduction
For More Information On This Product,
Preliminary
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
I/O
JTAG
TC[2:0]
DE
TMS
TCK
TDI
TDO
TRST
XTAL
EXTAL
POR
PLL
SIM
OnCE
CPU
SCI
OSC
(MPIO)
INTC
Timer1
CXFC
RESET
RSTOUT
UCLK
MPC7/URXD
MPC6/UTXD
MPC5/UCTS
MPC4/URTS
MPC3/TIC1
MPC2/TOC1
MPC1/TIC0
MPC0/TOC0
MPIO
SPI1-FSC
MPE4/LOCK
MPE3/MOSI
MPE2/MISO
MPE1/SS
MPE0/SCLK
MPB[7:4]/ROW[3:0]
MPB[3:0]/COL[3:0]
MPA[5:0]
CNFG
FLEX
Melody
BGNT
BREQ
MLDY
HIGHZ
PULL_EN
Arbiter
SPI0
MMC2080 Only
JTAG
I/O
Freescale Semiconductor, Inc...
MPD[7:0]/D[15:8]
D[7:0]
D[31:16]
A[21:0]
EB[1:0]
DVLEB[1:0]
BW8
WE
OE
TA
TEA
ABORT
BUSCLK
IRQ
DSTAT[5:0]
DVLMX
SEL[2:0], SEL3
DVLSEL
XBOOT
DVL[1:0]
SHS
Timer0
96K ROM
Peripheral Bus
System Bus
6K RAM
External
Bus
Bridge
APB
Keypad
LOBAT
EXTS[1:0]
CLKOUT
SYMCLK
S[7:1]
S0/IFIN
Figure 2. MMC2080/2075 DVL Block Diagram (208-Pin Package)
4
MMC2080/2075 Technical Data
For More Information On This Product,
Preliminary
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Conventions and Terminology
1.1 Conventions and Terminology
This document uses the following conventions:
•
•
•
•
•
•
•
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one
is a voltage that corresponds to Boolean true (1) state.
Logic level zero
is a voltage that corresponds to Boolean false (0) state.
To
set
a bit or bits means to establish logic level one.
To
clear
a bit or bits means to establish logic level zero.
A
signal
is an electronic construct whose state or changes in state convey information.
A
pin
is an external physical connection. The same pin can be used to connect a number of signals.
Asserted
means that a discrete signal is in active logic state.
—
Active low
signals change from logic level one to logic level zero.
—
Active high
signals change from logic level zero to logic level one.
•
Deasserted
means that an asserted discrete signal changes logic state.
—
Active low
signals change from logic level zero to logic level one.
—
Active high
signals change from logic level on to logic level zero.
•
LSB means
least significant bit
or
bits.
MSB means
most significant bit
or
bits.
References to low
and high bytes or words are spelled out.
Freescale Semiconductor, Inc...
Please refer to the examples in Table 1.
Table 1. Data Conventions
Signal/Symbol
PIN
PIN
PIN
PIN
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Introduction
For More Information On This Product,
Preliminary
Go to: www.freescale.com
5
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
