INTEGRATED CIRCUITS
DATA SHEET
SAA4978H
Picture Improved Combined
Network (PICNIC)
Product specification
Supersedes data of 1999 May 03
File under Integrated Circuits, IC02
2001 Apr 17
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
FUNCTIONAL DESCRIPTION
Analog input blocks
Gain elements for automatic gain control (9 dB
range)
Clamp circuit, clamping Y to digital level 32 and
UV to 0 (twos complement)
Analog anti-aliasing prefilter
9-bit analog-to-digital conversion
Digital processing blocks
Overflow detection
Y delay
Transient noise suppression
Non-linear phase filter after ADC
4 MHz notch
Digital clamp correction for UV
4 : 4 : 4 downsampled to 4 : 2 : 2 or 4 : 1 : 1
Bus A format: interface formatting, timed with
enabling signal (see Table 1 and Fig.9)
Bus B format (see Table 1 and Fig.9)
Time base correction and sample rate
conversion
Noise reduction
Histogram
Subtitle detection
Black bar detection
Bus C format (see Table 1)
Bus D reformatter: the various input formats
are all converted to the internal 9 bits 4 : 2 : 2
(see Table 1)
Peaking
Non-linear phase filter before DAC
DCTI
Border blank
Analog output blocks
Triple 10-bit digital-to-analog conversion
Analog anti-aliasing post-filter
PLL
SNERT
PSP
Microcontroller
Board level testability
Power-on reset
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
15
16
17
18
SAA4978H
CONTROL REGISTER DESCRIPTION
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
7.2.17
7.2.18
7.2.19
7.2.20
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
2001 Apr 17
2
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
1
FEATURES
SAA4978H
•
Clamp
•
Analog AGC
•
Triple YUV 9-bit Analog-to-Digital Converter (ADC)
•
Triple bypassable analog anti-alias filter
•
4 MHz notch filter
•
Non-linear phase filter after ADC
•
4 : 1 : 1 or 4 : 2 : 2 digital processing
•
4 : 1 : 1 or 4 : 2 : 2 selectable I/O interface
•
Asynchronous digital input
•
Time base correction
•
Histogram analysis
•
Histogram modification
•
Subtitle detection
•
Black bar detection
•
Line memory based noise reduction (spatial)
•
Noise level measurement
•
Clamp noise reduction
•
Dynamic peaking
•
Energy measurement
•
Multi Picture-In-Picture (multi PIP) decimation
•
Differential Pulse Code Modulation (DPCM) data
decompression for colour
3
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
f
clk
S/N
4
PARAMETER
analog supply voltage
digital supply voltage
analog supply current
digital supply current
clock frequency
signal-to-noise ratio
default settings
V
DDA
= 3.45 V
V
DDD
= 3.6 V
CONDITIONS
MIN.
3.15
3.0
−
−
−
50
TYP.
3.3
3.3
145
210
16
−
MAX.
3.45
3.6
180
270
−
−
UNIT
V
V
mA
mA
MHz
dB
•
2D-peaking and coring
•
Non-linear phase filter before DAC
•
Coaxial Transceiver Interface (CTI)
•
Triple 10-bit Digital-to-Analog Converter (DAC)
•
Triple bypassable analog reconstruction filter
•
Embedded microcontroller (80C51 core)
•
Programmable signal positioner
•
SNERT interface
•
I
2
C-bus user control interface
•
Boundary Scan Test (BST).
2
GENERAL DESCRIPTION
The SAA4978H is a monolithic integrated circuit suitable
either for 1f
H
or 2f
H
applications that contain a large variety
of picture improvement functions. It combines
analog-to-digital and digital-to-analog conversion for YUV
signals, digital processing, line-locked clock regeneration
and an 80C51 microcontroller core in one IC.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
QFP160
DESCRIPTION
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT322-2
SAA4978H
2001 Apr 17
3
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2001 Apr 17
VDDD1 to
VDDD4
VSSD1 to
VSSD4
BGEXT
17
64, 87,
100, 135
DIFFIN
21
64, 90,
134, 139
BAND GAP
REFERENCES
Ref L
Ref H
various
bias controls
YIN
23
Y
DELAY
MAJORITY
FOLLOWER
FILTER
CLAMP
25
UV
CLAMP
CORRECTION
TRIPLE
AGC
9-BIT
TRIPLE
ANALOG
PREFILTER
ADC
TRIPLE
9-BIT
UIN
VIN
26
CLP
OVERFLOW
DETECTOR
5
Philips Semiconductors
Picture Improved Combined Network
(PICNIC)
BLOCK DIAGRAM
WEA
YA0
to
YA8
UVA0
to
UVA8
UVB0
to
UVB8
YB0
to
YB8
WEB
CLKAS
62
53 to 61
3-STATE
43 to 51 84 to 76 75 to 67 66 85
SYNCHRONIZE
DITHER
NON-LINEAR
PHASE
FILTER
4 MHz
NOTCH
MUX
A
5
DITHER
MUX
REFORMATTER
5
FORMATTER
DOWNSAMPLER
11
10
DOWNSAMPLER
DITHER
UPSAMPLER
MUX
TIME BASE
CORRECTION/
SAMPLE
RATE
CONVERTER
B
4
VDDA1 to
VDDA4
VSSA1 to
VSSA4
11, 22, 24, 31
bus A
bus B
SKEWEN
SKEW
SAA4978H
13, 16, 27, 32
CLP
RED
WEA
BLANKING
BORDER
PIXREP
HREF
HA
C
D
WEC
IEC
BST/TEST
PSP
E
F
G
36
37
38
39
40
41
18
19
29
30
158
157
10
MHB172
TEST TRST TMS
TDI
TDO TCK
HDFL VDFL
VA
HREFEXT
INT1
INT0
FBL
Product specification
SAA4978H
Standard bus width in data path is 9 bits; exceptions are marked.
Fig.1 Block diagram (continued in Fig.2).
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2001 Apr 17
SPECTRAL
MEASUREMENT
NOISE
ESTIMATION
A
SUBTITLE
DETECTION
BLACK BAR
DETECTION
NOISE
REDUCTION
HISTOGRAM
MODIFICATION
B
Philips Semiconductors
Picture Improved Combined Network
(PICNIC)
YC8
to
WEC IEC YC0
UVC8
to
UVC0
UVD0
to
UVD8
YD0
to
YD8
RED
113
112
114 to 122
3-STATE
124 to 132
91
to 99
101 to 109
110
UNDITHER
DITHER
MUX
DOWNSAMPLER
DITHER
5
FORMATTER
MUX
SPECTRAL
MEASUREMENT
DYNAMIC 10
PEAKING
NON-LINEAR 10
PHASE
FILTER
12
YOUT
5
REFORMATTER
UPSAMPLER
10
MUX
DPCM DECODER
DCTI
10
BORDER
BLANK
DAC
TRIPLE
10-BIT
TRIPLE
ANALOG
POST-FILTER
14
UOUT
DITHER
8
DPCM
CODER
bus C
4
4
15
VOUT
bus D
PIXREP
BLANKING
BORDER
5
C
D
E
F
G
SPECIAL FUNCTION
REGISTERS
VARIOUS
REGISTERS
AUXILIARY
RAM
PROGRAM
ROM
SAA4978H
SKEWEN
CL16
CL16
CL16
HREF
SKEW
CL16
CL32
DATA8
P1.1
INT1 INT0 P1.4
80C51 MICROCONTROLLER CORE
bone
P1.5
WATCHDOG
FREQUENCY
GUARD
PLL
EA PSEN
P3.5 P3.4 P1.2 P1.3 P1.7 P1.6 RST
OR
1
2
140 149
to
to
147 156 136 137 138 160 159 8
9
5
4
6
7
42, 63, 86,
111, 133, 3
52, 123, 148
88
89
28
CRYSTAL
OSCILLATOR
34
35
MHB173
SNDA SNCL
P2.7 P0.7 EA
ALE
to
to
T1
PSEN
P2.0 P0.0
T0
RSTR
SCL
RST
RSTW
SDA
WDRST
VSSO1
to
VSSO6
VDDO1
to
VDDO3
CLK16 CLK32 HA
OSCI
OSCO
Product specification
SAA4978H
Standard bus width in data path is 9 bits; exceptions are marked.
Fig.2 Block diagram (continued from Fig.1).
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