Philips Semiconductors
Objective specification
Memory controller
FEATURES
•
Support for acquisition, display and deflection PLL
•
50/100 Hz (or 60/120 Hz) scan conversion
•
Progressive scan 50 Hz/1250 lines (60 Hz/1050 lines)
interlaced or 50 Hz/625 lines (60 Hz/525 lines)
non-interlaced in serial memory structure
•
50 Hz/625 lines (60 Hz/525 lines) mode support for a
PALplus system and basic features
•
Acquisition frequencies 12, 13.5, 16 and 18 MHz and
display frequencies of 27, 32 and 36 MHz (2f
H
) in every
combination, horizontal compression (support for 4 : 3
and 14 : 9 display on a 16 : 9 screen) and horizontal
zoom
•
Configured as a three clock system with a fixed 27 MHz
deflection clock (deflection controlled by the TDA9151)
•
Configured as a two-clock system (deflection controlled
by e.g. TDA9152)
•
Single clock for 50 Hz vertical and 15.625 kHz
horizontal frequency
•
Support of new IC generations [PAN-IC (SAA4995WP),
VERIC (SAA4997H), MACPACIC (SAA4996H) and
LIMERIC (SAA4945H)]
•
Support for two or one field memories
•
Still picture
•
Support for memory types such as TMS4C2970/71
•
Internal simple Multi-PIP (3
×
3) or (4
×
4) conversion
•
Multi-PIP support with an external PIP module/full
performance
•
Programmable via microcontroller port
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
f
LLDFL,LLD
f
acq
T
amb
supply voltage
supply current
operating frequency of display and deflection part
acquisition frequency
operating ambient temperature
PARAMETER
MIN.
4.5
−
−
−
0
SAA4952WP
•
Capability of reading the length of incoming fields via
microcontroller port
•
Golden SCART option (clock generation for TDA9151)
•
Acquisition is able to operate with external sync and
clock of digital sources (slave mode)
•
Generator mode for the display, stable still picture or
OSD in the event of no input source.
GENERAL DESCRIPTION
The memory controller SAA4952WP is the improved
version of the SAA4951WP. The circuit has been designed
for high-end TV sets using 2f
H
technics. For basic feature
modules a 1f
H
mode can be activated. In this situation the
controller supplies the system with a line-locked clock.
The new device has been designed to be able to operate
in the hardware environment of the SAA4951WP.
The circuit provides all necessary write, read and clock
pulses to control different field memory concepts.
Furthermore the drive signals for the horizontal and
vertical deflection power stages are also generated.
The device is connected to a microcontroller via an 8-bit
data bus. The microcontroller receives commands via the
I
2
C-bus. Due to this fact the START and STOP conditions
of the main output control signals are programmable and
the SAA4952WP can be set in different function modes
depending on the TV feature concept that is used.
TYP.
5
35
−
−
−
MAX.
5.5
−
33
37
85
UNIT
V
mA
MHz
MHz
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA4952WP
PLCC44
DESCRIPTION
plastic leaded chip carrier; 44 leads
VERSION
SOT187-2
1997 Jun 10
2
Philips Semiconductors
Objective specification
Memory controller
PINNING
SYMBOL
HRD
V
DD1
SWC1
SRC
SDP
SWC05
IE1
WE1
STROBE
V
DD2
HRA/BLNA
V
SS1
LLA
IE2
WE2
CLV
HVCD
RE1
RE2
BLND
ALE
WRD
V
DD3
V
SS2
P0
P1
P2
P3
P4
P5
P6
P7
LLDFL
V
SS3
HRDFL
V
DD4
HDFL
VDFL
VACQ
1997 Jun 10
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
I/O
O
supply
O
O
I
O
O
O
I
supply
I/O
−
I
O
O
O
O
O
O
O
I
I
supply
−
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
−
O
supply
O
O
I
supply voltage 1
serial write clock output for memory 1
serial read clock output
select deflection processor input
serial write clock output, SWC1 divided-by-2
input enable signal output (memory 1)
write enable signal output (memory 1)
strobe signal input
supply voltage 2
DESCRIPTION
horizontal reference signal output (display PLL)
SAA4952WP
horizontal reference signal output (acquisition part)/horizontal blanking
signal input, reset for horizontal acquisition counters (acquisition part)
ground 1
line-locked clock signal input (acquisition part)
input enable signal output (memory 2)
write enable signal output (memory 2)
horizontal signal output (acquisition part)
horizontal, vertical or composite blanking signal output (display part)
read enable signal output (memory 1)
read enable signal output (memory 2)
horizontal blanking signal output (display part)
address latch enable signal input
write/read data signal input
supply voltage 3
ground 2
data input/output signal bit 0
data input/output signal bit 1
data input/output signal bit 2
data input/output signal bit 3
data input/output signal bit 4
data input/output signal bit 5
data input/output signal bit 6
data input/output signal bit 7 (MSB = Most Significant Bit)
line-locked clock signal input (deflection part)
ground 3
horizontal reference signal output (deflection part)
supply voltage 4
horizontal synchronization signal output (deflection part)
vertical synchronization signal output (deflection part)
vertical synchronization signal input (acquisition part)
4
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