INTEGRATED CIRCUITS
DATA SHEET
SAA2003
Stereo filter and codec
Preliminary specification
File under Integrated Circuits, IC01
May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Stereo filter and codec
FEATURES
•
Single-chip stereo filter and codec
•
Wide operating voltage range: 2.7 to 5.5 V
•
Low-power consumption: 98 mW; 3.0 V
•
Sleep mode for low power and low Electromagnetic
Interference (EMI)
•
Transparent serial audio data mode in sleep
•
IEC 958 digital output
•
Peak level detector for start of track detection or
VU meter
•
Versatile fade processor; slow/fast fade, mute,
12 dB attenuation
•
Serial audio interface for I
2
S or EIAJ formats
•
Error concealment
•
Three-wire L3 bus microcontroller interface
•
Three sample rates:
– 32 kHz
– 44.1 kHz
– 48 kHz
•
Internal or external clock source
•
Three programmable outputs
•
Small surface mounted package (SOT307).
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA2003H
Note
PACKAGE
PINS
44
PIN POSITION
QFP
(1)
MATERIAL
plastic
GENERAL DESCRIPTION
SAA2003
The SAA2003 performs the sub-band filtering and audio
frame codec functions in the Precision Adaptive Sub-band
Coding (PASC) system. It can be used as a stand-alone
decoder for playback only applications, but requires the
addition of an Adaptive Allocation and Scale Factor
processor (SAA2013) in order to perform PASC encoding
in a DCC record system.
CODE
SOT307
1. When using reflow soldering it is recommended that the Dry Packing instructions in the
“Quality Reference
Pocketbook”
are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Stereo filter and codec
BLOCK DIAGRAM
SAA2003
handbook, full pagewidth
X22OUT
X24OUT
CLK24
FS256
X22IN
X24IN
CLK22
X256
6
5
10
9
4
11
37
38
VDD1 V DD2 VDD3
28
7
39
32
MUTEDAC
31
ATTDAC
DEEMDAC
CLOCK GENERATOR
TEST0
TEST1
IECOP
19
20
29
IEC 958
OUTPUT
FS128
6.15 MHz
FS256
SBMCLK
30
25
SBWS
WS
SCK
SD1
SD2
34
33
36
35
BASEBAND
SERIAL
INTERFACE
AND
PEAK
DETECTOR
SUBBAND
SERIAL
INTERFACE
24
23
22
26
SBCL
SBDA
SBDIR
SBEF
SAA2003
STEREO SUBBAND
FILTER PROCESSOR
PASC CODEC
PROCESSOR
21
FILTERED DATA
INTERFACE
MICROCONTROLLER
INTERFACE AND CONTROL
13
12
URDA
RESET
SLEEP
27
8
40
43
2
FDCL
3
44
FDAO
1
17
LTCNT0
18
14
15
16
41
42
MBD618
V SS1 V SS2 V SS3
L3DATA
L3MODE
SYNCDAI
FSYNC
FDWS
FDAI
LTCNT1
L3CLK
FDIR
Fig.1 Block diagram.
May 1994
3
Philips Semiconductors
Preliminary specification
Stereo filter and codec
PINNING
SYMBOL
FDAI
FDCL
FDWS
CLK22
X22OUT
X22IN
V
DD2
V
SS2
X24OUT
X24IN
CLK24
SLEEP
RESET
L3DATA
L3CLK
L3MODE
LTCNT0
LTCNT1
TEST0
TEST1
URDA
SBDIR
SBDA
SBCL
SBWS
SBEF
V
SS1
V
DD1
IECOP
DEEMDAC
ATTDAC
MUTEDAC
SD2
SD1
SCK
WS
X256
FS256
V
DD3
V
SS3
May 1994
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
filtered data bit clock
filtered data word select
22.5792 MHz buffered clock output
22.5792 MHz crystal output
22.5792 MHz crystal input
supply voltage (clock oscillator)
supply ground (clock oscillator)
24.576 MHz crystal output
24.576 MHz crystal input
24.576 MHz buffered clock output
sleep mode; device inactive
device reset
3-wire interface; serial data
3-wire interface; bit clock
3-wire interface; mode control
LT interface; control bit 0
LT interface; control bit 1
test mode select
test mode select
unreliable data flag from drive processor
sub-band data direction
sub-band serial data
sub-band bit clock
sub-band word select
sub-band error flag from drive processor
digital supply ground
digital supply voltage
IEC 958 digital audio output
DAC control or general purpose output
DAC control or general purpose output
DAC control or general purpose output
serial audio data to DAC
serial audio data to/from DAIO and DAC
serial audio data bit clock
serial audio data word select
master audio clock from external source
master audio clock at 256 times sample frequency
supply voltage (FS256)
supply ground (FS256)
4
DESCRIPTION
filtered data input from SAA2013
SAA2003
TYPE
I
O
O
O
O
I
−
−
O
I
O
I
I
I/O
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I
−
−
O
O
O
O
O
I/O
I/O
I/O
I
O
−
−
Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
FDIR
SYNCDAI
FSYNC
FDAO
PIN
41
42
43
44
DESCRIPTION
filter direction; encode or decode
settings synchronization for DAIO
sub-band 0 sample synchronization for SAA2013
filtered data output to SAA2013
TYPE
O
O
O
O
42 SYNCDAI
43 FSYNC
38 FS256
44 FDAO
39 VDD3
40 VSS3
41 FDIR
37 X256
35 SCK
FDAI
FDCL
FDWS
CLK22
X22OUT
X22IN
VDD2
VSS2
X24OUT
1
2
3
4
5
6
7
8
9
34 SD1
36 WS
33 SD2
32 MUTEDAC
31 ATTDAC
30 DEEMDAC
29 IECOP
SAA2003
28 VDD1
27 VSS1
26 SBEF
25 SBWS
24 SBCL
23 SBDA
MBD619
X24IN 10
CLK24 11
TEST1 20
URDA 21
SLEEP 12
RESET 13
L3DATA 14
L3CLK 15
L3MODE 16
LTCNT0 17
LTCNT1 18
Fig.2 Pin configuration.
May 1994
5
SBDIR 22
TEST0 19
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