Features
•
PowerPC
®
Single Issue Integer Core
•
Precise Exception Model
•
Extensive System Development Support
– On-chip Watchpoints and Breakpoints
– Program Flow Tracking
– On-chip Emulation (Once) Development Interface
High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)
Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)
MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus
Monitor, and Real-time Clocks
Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with
Book 1 of the PowerPC Architecture Definition) with 32 x 32-bit Fixed Point Registers
– Embedded PowerPC Performs Branch Folding, Branch Prediction with
Conditional Prefetch, without Conditional Execution
– 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU
– Instruction and Data Caches are Two-way, Set Associative, Physical Address,
4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line
Granularity
– MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs
– MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB;
16 Virtual Address Spaces and 8 Protection Groups
– Advanced On-chip Emulation Debug Mode
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)
32 Address Lines
Fully Static Design
V
CC
= +3.3V ± 5%
f
max
= 66 MHz (80 MHz (TBC))
Military Temperature Range: -55°C < T
C
< +125°C
P
D
= 0.75 W Typical at 66 MHz
•
•
•
•
32-bit Quad
Integrated
Power QUICC™
Communication
Controller
TSPC860
•
•
•
•
•
•
•
Description
The TSPC860 PowerPC QUad Integrated Communication Controller (Power
QUICC
™
) is a versatile one-chip integrated microprocessor and peripheral combina-
tion that can be used in a variety of controller applications. It particularly excels in
communications and networking systems. The Power QUICC (pronounced “quick”)
can be described as a PowerPC-based derivative of the TS68EN360 (QUICC
™
).
The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates
memory management units (MMUs) and instruction and data caches. The communi-
cations processor module (CPM) of the TS68EN360 QUICC has been enhanced with
the addition of a Two-wire Interface (TWI) compatible with protocols such as I
2
C. Mod-
erate to high digital signal processing (DSP) functionality has been added to the CPM.
The memory controller has been enhanced, enabling the TSPC860 to support any
type of memory, including high performance memories and newer dynamic random
access memories (DRAMs). Overall system functionality is completed with the addi-
tion of a PCMCIA socket controller supporting up to two sockets and a real-time clock.
PBGA 357
ZP suffix
Rev. 2129A–HIREL–08/02
1
Screening/Quality
This product will be manufactured in full compliance with:
•
According to Atmel Standards
The TSPC860 is functionally composed of three major blocks:
•
•
•
A 32-bit PowerPC Core with MMUs and Caches
A System Interface Unit
A Communications Processor Module
General Description
Figure 1.
Block Diagram View of the TSPC860
4 or 16 KB
I-Cache
SYSTEM INTERFACE UNIT
Memory Controller
Unified Bus
Bus Interface Unit
Embedded
PowerPC
Core
Instruction
Bus
I-MMU
4 or 8 KB
D-Cache
System Functions
Real Time Clock
PCMCIA Interface
Load/store
BUS
4
Timers
D-MMU
Parallel I/O
Baud Rate
Generators
Parallel
Interface Port
Interrupt
Controller
Dual-Port
RAM
16 Serial DMA
and
Virtual IDMA
32-bit RISC µController
and Program ROM
MAC
Timer
SCC1
SCC2
SCC3
SCC4
SMC1 SMC2
SPI
TWI
Time Slot Assigner
Serial Interface
2
TSPC860
2129A–HIREL–08/02
TSPC860
Main Features
The Following is a List of the TSPC860’s Important Features:
•
•
•
•
•
•
•
•
Fully Static Design
Four Major Power Saving Modes
357 OMPAC Ball Grid Array Packaging (Plastic)
32-bit Address and Data Busses
Flexible Memory Management
4-Kbyte Physical Address, Two-way, Set-associative Data Cache
4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache
Eight-bank Memory Controller
–
–
–
•
–
–
–
–
–
–
–
–
•
–
–
–
–
–
–
Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals
Byte Write Enables and Selectable Parity Generation
32-bit Address Decodes With Bit Masks
Clock Synthesizer
Power Management
Reset Controller
PowerPC Decrementer And Time Base
Real-time Clock Register
Periodic Interrupt Timer
Hardware Bus Monitor and Software Watchdog Timer
IEEE 1149.1 JTAG Test Access Port
Embedded 32-bit RISC Controller Architecture for Flexible I/O
Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual
DMA Channel Controller
Continuous Mode Transmission And Reception On All Serial Channels
Serial DMA Channels For Reception And Transmission On All Serial
Channels
I/O registers with Open-drain and Interrupt Capability
Memory-memory and Memory-I/O Transfers with Virtual DMA Functionality
System Interface Unit
Communications Processor Module
3
2129A–HIREL–08/02
–
Protocols Supported by ROM or Downloadable Microcode and Include, but
Limited to, the Digital Portion of:
- Ethernet/IEEE 802.3 CS/CDMA
- HDLC2/SDLC and HDLC bus
- Apple Talk
- Signaling System #7 (RAM Microcode Only)
- Universal Asynchronous Receiver Transmitter (UART)
- Synchronous UART
- Binary Synchronous (BiSync) Communications
- Totally Transparent
- Totally Transparent with CRC
- Profibus (RAM Microcode Option)
- Asynchronous HDLC
- DDCMP
- V.14 (RAM Microcode Option)
- X.21 (RAM Microcode Option)
- V.32bis Datapump Filters
- IrDA Serial Infrared
- Basis Rate ISDN (BRI) in Conjunction with SMC Channels
- Primary Rate ISDN (MH Version Only)
Four Hardware Serial Communications Controller Channels Supporting the
Protocols
Two Hardware Serial Management Channels
- Management for BRI Devices as General Circuit Interface Controller
Multiplexed Channels
- Low-speed UART operation
Hardware Serial Peripheral Interfaces
Two-wire Interface (TWI)
Time-slot Assigner
Port Supports Centronics Interfaces and Chip-to-chip
Four Independent Baud Rate Generators and Four Input Clock Pins for
Supplying Clocks to SMC and SCC Serial Channels
Four Independent 16-bit timers Which Can Be Interconnected as Two 32-bit
Timers
–
–
–
–
–
–
–
–
4
TSPC860
2129A–HIREL–08/02
TSPC860
Pin Assignment
Plastic Ball Grid Array
Figure 2.
Pin Assignment: Top View
W
PD10
PD8
PD3
IRQ7
D0
D4
D1
D2
D3
D5
VDDL
D6
D7
D29
DP2 CLKOUT IPA3
V
PD14
PD13
PD9
PD6
M_Tx_EN IRQ0 D13
D27
D10
D14
D18
D20
D24
D28
DP1
DP3
DP0
N/C VSSSYN1
U
PA0
PA1
PB14 PD15
PC5
PC4
PD4
PD11
PD5
PD7
IRQ1
D8
D23
D17
D11
D9
D16
D15
D19
D22
D21
D25
D26
D31
D30
IPA6
IPA5
IPA0
IPA4
IPA1
IPA2
IPA7
N/C VSSSYN
T
VDDH D12
VDDH
XFC VDDSYN
PC6
PA2
PB15
PD12
R
VDDH
WAIT_B WAIT_A
PORESET
KAPWR
P
PA4
PB17
PA3
VDDL
GND
GND
VDDL RSTCONF SRESET XTAL
N
HRESET
TEXP
EXTCLK EXTAL
M
PB19
PA5
PB18
PB16
PA7
PC8
PA6
PC7
MODCK2
BADDR28
BADDR29 VDDL
L
PB22
PC9
PA8
PB20
OP0
AS
OP1 MODCK1
K
PC10
PA9
PB23
PB21
GND
BADDR30 IPB6 ALEA
IRQ4
J
PC11
PB24
PA10
PB25
IPB5
IPB1
IPB2
ALEB
H
VDDL M_MDIO TDI
TCK
M_COL IRQ2
IPB0
IPB7
G
TRST
TMS
TDO
PA11
GND
VDDH
GND
VDDH
BR
IRQ6
IPB4
IPB3
F
PB26
PC12
PA12 VDDL
VDDL
TS
IRQ3 BURST
E
PB27
PC13
PA13
PB29
CS3
BI
BG
BB
D
PB28
PC14
PA14
PC15
A8
N/C
N/C
A15
A19
A25
A18
BSA0 GPLA0
N/C
CS6
CS2 GPLA5 BDIP
TEA
C
PB30
PA15
PB31
A3
A9
A12
A16
A20
A24
A26
TSIZ1 BSA1
WE0 GPLA1 GPLA3 CS7
CS0
TA
GPLA4
B
A0
A1
A4
A6
A10
A13
A17
A21
A23
A22
TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5
CE1A
WR
GPLB4
A
A2
19
18
A5
17
A7
16
A11
15
A14
14
A27
13
A29
12
A30
11
A28
10
A31
9
VDDL BSA2
8
7
WE1
6
WE3
5
CS4
4
CE2A
3
CS1
2
1
Signal Descriptions
This section describes the signals on the TSPC860.
5
2129A–HIREL–08/02
FPGA/CPLD
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