TH50VSF3580/3581AASB
TENTATIVE
TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
DESCRIPTION
The TH50VSF3580/3581AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a
33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration.
The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write
or Erase operation. The TH50VSF3580/3581AASB can range from 2.7 V to 3.3 V. The TH50VSF3580/3581AASB is
available in a 69-pin BGA package, making it suitable for a variety of design applications.
FEATURES
•
•
•
Power supply voltage
V
CCs
=
2.7 V~3.3 V
V
CCf
=
2.7 V~3.3 V
Data retention supply voltage
V
CCs
=
1.5 V~3.3 V
Current consumption
Operating: 45 mA maximum (CMOS level)
Standby: 10
µA
maximum (SRAM CMOS level)
Standby: 10
µA
maximum (FLASH)
Block erase architecture for flash memory
8
×
8 Kbytes
63
×
64 Kbytes
Organization
CIOF
V
CC
V
CC
V
SS
CIOS
V
CC
V
SS
V
SS
Flash Memory
2,097,152 words of 16 bits
2,097,152 words of 16 bits
4,194,304 words of 8 bits
SRAM
524,288 words of 16 bits
1,048,576 words of 8 bits
1,048,576 words of 8 bits
•
•
•
•
•
•
•
PIN ASSIGNMENT
(TOP VIEW)
•
Case: CIOF
=
V
CC
, CIOS
=
V
CC
(×16,
×16)
1
2
3
4
5
6
7
8
9
10
Function mode control for flash memory
Compatible with JEDEC-standard commands
Flash memory functions
Simultaneous Read/Write operations
Auto-Program
Auto Chip Erase, Auto Block Erase
Auto Multiple-Block Erase
Program Suspend/Resume
Block-Erase Suspend/Resume
Data Polling/Toggle Bit function
Block Protection/Boot Block Protection
Automatic Sleep, Hidden ROM Area Supports
Common Flash Memory Interface (CFI)
Byte/Word Mode
Erase and Program cycle for flash memory
10
5
cycles (typical)
Boot block architecture for flash memory
TH50VSF3580AASB: Top boot block
TH50VSF3581AASB: Bottom boot block
Package
P-FBGA69-1209-0.80A3: 0.31 g (typ.)
PIN NAMES
A0~A21
A12S
A12F
SA
DQ0~DQ15
CEF
OE
Address Inputs
A12 Input for SRAM
A12 Input for Flash Memory
A18 Input for SRAM
Data Inputs/Outputs
Chip Enable Input for Flash Memory
Output Enable Input
Write Enable Input
Data Byte Control Input
Ready/Busy Output
Hardware Reset Input
Write Protect/Program Acceleration Input
Word Enable Input for SRAM
Word Enable Input for Flash Memory
Power Supply for SRAM
Power Supply for Flash Memory
Ground
Not Connected
Don’t Use
000707EBA2
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
NC
A3
A2
NC
NC
A1
A0
CEF
CE1S
A7
A6
A5
A4
V
SS
OE
DQ0
DQ8
NC
NC
NC
NC
CE1S , CE2S Chip Enable Inputs for SRAM
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
WP/ACC
RESET
WE
CE2S
A20
A8
A19
A9
A10
DQ6
A11
A12
A13
A14
DU
A15
NC
NC
A16
NC
NC
WE
LB
, UB
RY/BY
RESET
WP/ACC
CIOS
CIOF
V
CCs
V
CCf
NC
NC
V
SS
NC
DU
RY/BY
DQ3
V
CCf
DQ11
DQ4
DQ13 DQ15 CIOF
DQ7
DQ14
V
SS
V
CCs
DQ12
CIOS
DQ5
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
2001-03-06 1/50
TH50VSF3580/3581AASB
COMMAND SEQUENCES
BUS
COMMAND
SEQUENCE
WRITE
CYCLES
REQ’D
Read/Reset
Read/Reset
Word
Byte
Word
ID Read
Byte
Word
Byte
Program Suspend
Program Resume
Auto Chip
Erase
Auto Block
Erase
Word
Byte
Word
Byte
1
1
4
Word
3
Byte
Fast Program
Set
Fast Program
Fast Program Reset
Hidden ROM
Mode Entry
Hidden ROM
Program
Hidden ROM
Erase
Hidden ROM
Mode Exit
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
2
Byte
4
6
4
Word
Byte
2
2
3
AAAH
555H
AAAH
XXXH
XXXH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
BK
BK
(3)
FIRST BUS
WRITE CYCLE
Addr.
XXXH
555H
AAAH
555H
Data
F0H
AAH
SECOND BUS
WRITE CYCLE
Addr.
Data
THIRD BUS
WRITE CYCLE
Addr.
Data
FOURTH BUS
WRITE CYCLE
Addr.
Data
FIFTH BUS
WRITE CYCLE
Addr.
Data
SIXTH BUS
WRITE CYCLE
Addr.
Data
1
3
2AAH
555H
2AAH
55H
555H
AAAH
BK
(3)
F0H
RA
(1)
RD
(2)
+
+
90H
IA
(4)
3
AAAH
555H
AAAH
1
1
6
BK
BK
(3)
(3)
AAH
555H
2AAH
555H
B0H
30H
AAH
2AAH
555H
AAH
B0H
30H
60H
BPA
(9)
55H
555H
BK
(3)
ID
(5)
AAAH
55H
555H
AAAH
A0H
PA
(6)
Auto-Program
4
AAH
PD
(7)
555H
AAAH
55H
555H
AAAH
80H
555H
AAAH
AAH
2AAH
555H
55H
555H
AAAH
10H
6
555H
AAAH
BK
BK
(3)
(3)
2AAH
555H
55H
555H
AAAH
80H
555H
AAAH
AAH
2AAH
555H
55H
BA
(8)
30H
Block Erase Suspend
Block Erase Resume
Block Protect
XXXH
555H
60H
XXXH
BK
+
555H
(3)
(3)
40H
BPA
(9)
BPD
(10)
Verify Block
Protect
2AAH
AAH
555H
2AAH
555H
A0H
90H
AAH
PA
(6)
55H
BK
+
90H
BPA
(9)
BPD
(10)
AAAH
55H
PD
F0H
(7)
3
AAH
555H
AAAH
20H
XXXH
2AAH
555H
(13)
55H
555H
AAAH
88H
(6)
(7)
AAH
2AAH
555H
55H
555H
AAAH
A0H
PA
PD
AAH
2AAH
555H
55H
555H
AAAH
80H
555H
AAAH
AAH
2AAH
555H
55H
BA
(8)
30H
AAH
2AAH
555H
55H
555H
AAAH
90H
XXXH
00H
+
+
98H
CA
(11)
Query
Command
55H
(3)
CD
(12)
AAH
Note: The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A10~A0
Byte Mode: AAAH or 555H to addresses A10~A0, A12F
DQ8~DQ15 are ignored in Word mode.
•
Byte mode when V
IL
is inputted to CIOF, and addresses
are A21~A0
•
Write mode when V
IH
is inputted to CIOF, and addresses
are A20~A0
•
Valid addresses are A10~A0 when a command is entered.
(6) PA: Program Address
(1) RA: Read Address
(2) RD: Read Data
(7) PD: Program Data
(3) BK: Bank Address
=
A20~A15
(8) BA: Block Address
=
A20~A12
(4) IA: Bank Address and ID Read Address (A6, A1, A0) (9) BPA: Block Address and ID Read Address (A6, A1, A0)
Bank Address
=
A20~A15
Block Address
=
A20~A12
Manufacturer Code
=
(0, 0, 0)
ID Read Address
=
(0, 1, 0)
Device Code
=
(0, 0, 1)
(10) BPD: Verify Data
(5) ID: ID Data
(11) CA: CFI Address
0098H - Manufacturer Code
(12) CD: CFI Data
009AH - Device Code (TH50VSF3580AASB)
(13) F0H: 00H is valid too
009CH - Device Code (TH50VSF3581AASB)
0001H - Protected Block
2001-03-06 5/50
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