电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

CY74FCT163543CPVC

产品描述Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56
产品类别逻辑    逻辑   
文件大小108KB,共5页
制造商Cypress(赛普拉斯)
下载文档 详细参数 选型对比 全文预览

CY74FCT163543CPVC概述

Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56

CY74FCT163543CPVC规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码SSOP
包装说明0.300 INCH, 0.025 INCH PITCH, SSOP-56
针数56
Reach Compliance Code_compli
其他特性WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型INDEPENDENT CONTROL
计数方向BIDIRECTIONAL
系列FCT
JESD-30 代码R-PDSO-G56
JESD-609代码e0
长度18.415 mm
负载电容(CL)50 pF
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
最大I(ol)0.024 A
位数8
功能数量2
端口数量2
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码SSOP
封装等效代码SSOP56,.4
封装形状RECTANGULAR
封装形式SMALL OUTLINE, SHRINK PITCH
电源3/3.3 V
Prop。Delay @ Nom-Su5.1 ns
传播延迟(tpd)5.6 ns
认证状态Not Qualified
座面最大高度2.794 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.635 mm
端子位置DUAL
翻译N/A
宽度7.5 mm
Base Number Matches1

文档预览

下载PDF文档
1CY 74FCT1 635 43
fax id: 7057
CY74FCT163543
16-Bit Latched Transceiver
Features
• 5V tolerant Inputs and Outputs
• 24 mA balanced drive outputs
• Low power, pin-compatible replacement for
LCX, LPT, LVC, LVCH & LVT families
• FCT-C speed at 5.1 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Extended commercial temperature range of
–40°C to +85°C
• V
CC
= 3.3V ± 0.3V Normal Range
• V
CC
= 2.7V to 3.6V Extended Range
• Typical V
OLP
(ground bounce) <0.3V
at V
CC
= 3.3V, T
A
= 25°C
• Input hysteresis of 100 mV
Functional Description
The CY74FCT163543 is a 16-bit, high-speed, low power latched
transceiver that is organized as two independent 8-bit D-type latched
transceivers, containing two sets of eight D-type latches with sepa-
rate Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB)
controls for each set to permit independent control of inputting and
outputting in either direction of data flow. For data flow from A to B, for
example, the A-to-B input Enable (CEAB) must be LOW in order to
enter data from A or to take data from B, as indicated in the truth table.
With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB)
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode
and their outputs no longer follow the A inputs. With CEAB and OEAB
both LOW, the three-state B output buffers are active and reflect the
data present at the output of the A latches. Control of data from B to
A is similar, but uses CEAB, LEAB, and OEAB inputs.
The CY74FCT163543 has 24-mA balanced output drivers with
current limiting resistors in the outputs. This reduces the need
for external terminating resistors and provides for minimal un-
dershoot and reduced ground bounce. The inputs and outputs
are capable of being driven by 5.0V buses, allowing them to
be used in mixed voltage systems as translators. The outputs
are also designed with a power off disable feature enabling
them to be used in applications requiring live insertion.
Flow-through pinout and small shrink packaging simplify board de-
sign
Logic Block Diagrams
OEBA
1
1
CEBA
1
LEBA
1
OEAB
1
CEAB
1
LEAB
Pin Configuration
Top View
SSOP/TSSOP
1
OEAB
1
LEAB
1
CEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
LEBA
1
CEBA
A
1 1
C
D
C
D
GND
1
A
1
1
B
1
1
A
2
V
CC
1
A
3
1
A
4
1
A
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
1
1
B
2
V
CC
1
B
3
1
B
4
1
B
5
TO 7 OTHER CHANNELS
2
OEBA
2
CEBA
2
LEBA
2
OEAB
2
CEAB
2
LEAB
2
A
1
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
GND
2
A
4
2
A
5
C
D
C
D
2
A
6
V
CC
2
A
7
2
A
8
GND
2
B
4
2
B
5
2
B
6
2
B
1
V
CC
2
B
7
2
B
8
GND
2
CEBA
2
LEBA
2
OEBA
GND
2
CEAB
2
LEAB
2
OEAB
TO 7 OTHER CHANNELS
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 3, 1997

CY74FCT163543CPVC相似产品对比

CY74FCT163543CPVC CY74FCT163543APVC CY74FCT163543CPAC CY74FCT163543APAC
描述 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56
是否Rohs认证 不符合 不符合 不符合 不符合
零件包装代码 SSOP SSOP TSSOP TSSOP
包装说明 0.300 INCH, 0.025 INCH PITCH, SSOP-56 0.300 INCH, 0.025 INCH PITCH, SSOP-56 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56
针数 56 56 56 56
Reach Compliance Code _compli _compli _compli _compli
其他特性 WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型 INDEPENDENT CONTROL INDEPENDENT CONTROL INDEPENDENT CONTROL INDEPENDENT CONTROL
计数方向 BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL
系列 FCT FCT FCT FCT
JESD-30 代码 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609代码 e0 e0 e0 e0
长度 18.415 mm 18.415 mm 14 mm 14 mm
负载电容(CL) 50 pF 50 pF 50 pF 50 pF
逻辑集成电路类型 REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
最大I(ol) 0.024 A 0.024 A 0.024 A 0.024 A
位数 8 8 8 8
功能数量 2 2 2 2
端口数量 2 2 2 2
端子数量 56 56 56 56
最高工作温度 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SSOP SSOP TSSOP TSSOP
封装等效代码 SSOP56,.4 SSOP56,.4 TSSOP56,.3,20 TSSOP56,.3,20
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V
Prop。Delay @ Nom-Su 5.1 ns 6.5 ns 5.1 ns 6.5 ns
传播延迟(tpd) 5.6 ns 8 ns 5.6 ns 8 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 2.794 mm 2.794 mm 1.1 mm 1.1 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES
技术 CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 GULL WING GULL WING GULL WING GULL WING
端子节距 0.635 mm 0.635 mm 0.5 mm 0.5 mm
端子位置 DUAL DUAL DUAL DUAL
翻译 N/A N/A N/A N/A
宽度 7.5 mm 7.5 mm 6.1 mm 6.1 mm
Base Number Matches 1 1 1 1
关于锅仔片PCB设计要求的一些问题
公司现在要对PCB设计进行规范化要求。 哪位大虾有锅仔片PCB设计方面的经验,分享下 主要是锅仔片的PCB设计原则,比如圆形锅仔片的外径内径间隔等原则,铺铜高度,阻罕层,穿孔的位置等等。 ......
chenlei59 PCB设计
问下关于电涌保护器
关于这个电涌保护器/防雷保护器,这个东西跟压敏电阻有什么区别吗? 假如在380V进线处,每条相线跟零线之间并一个压敏电阻,效果是不是就一样了? 422489 ...
sky999 电源技术
寻找一名兼职STM32工程师
我们现有一51单片机产品需要升级为STM32,现需要一名兼职嵌入式工程师协助完成以下工作:电路及电路板设计、程序设计。要求:居住在北京市,有嵌入式产品的相关经验。报酬:报酬优厚,详情请面 ......
jj4531 求职招聘
CC2530+CC2591TI官方参考设计
CC2530+CC2591TI官方参考设计 ...
1185054154 微控制器 MCU
串口转网口,IP获得时间
我用LM3S6432芯片,调用lwIPLocalIPAddrGet函数,获得网口IP,但实际 需要30秒的时间,该函数才会返回IP值,这正常吗?...
victorzifeng 微控制器 MCU
今天早晨门口发的免费地瓜券
有人打电话送货了没?呵呵...
pleasant 聊聊、笑笑、闹闹

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 453  287  801  2670  2065  10  6  17  54  42 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved