NCP5383
2 Phase Buck Controller
with Integrated Gate
Drivers and AVP
The NCP5383 is a two phase buck controller used in low voltage,
high current power supplies. Dual-edge pulse-width modulation
(PWM) combined with inductor current sensing and adaptive voltage
positioning (AVP) reduces system cost by providing the fastest initial
response to transient loads thereby requiring less bulk and ceramic
output capacitors to satisfy transient load-line requirements.
A high performance operational error amplifier is provided, which
allows for easy compensation of the system. Protection features
include overcurrent protection, undervoltage lockout (UVLO),
thermal shutdown and power good monitor.
Features
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MARKING
DIAGRAM
1
24 PIN QFN, 4x4
MN SUFFIX
CASE 485L
5383
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
•
Dual-edge PWM for Fastest Initial Response to Transient Loading
High Performance Operational Error Amplifier
1% Internal Reference Voltage Accuracy
Phase-to-Phase Current Balancing
“Lossless” Differential Inductor Current Sensing
Differential Current Sense Amplifiers for Each Phase
Adaptive Voltage Positioning (AVP)
Frequency Range: 100 kHz – 400 kHz Set by the Resistor
Power Good Output with Internal Delays
Programmable Soft Start Time
Integrated Gate Drivers
This is a Pb-Free Device
5383
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
PG
BST1
TG1
SWN1
PGND1
BG1
R
OSC
I
LIM
V
CC
AGND
SS
COMP
V
FB
V
DRP
CS1
CSN
CS2
EN
(Top View)
V
CCP
BG2
PGND2
SWN2
TG2
BST2
Applications
•
Pentium IV Processors
•
Graphics Cards
•
Low Voltage, High Current Power Supplies
ORDERING INFORMATION
Device
NCP5383MNR2G
Package
Shipping
†
QFN-24 4000 / Tape & Reel
(Pb-Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2007
1
December, 2007 - Rev. 3
Publication Order Number:
NCP5383/D
NCP5383
SS
V
core
2
FAULT
SS
23
BST1
OVP (125% of V
FB
)
UVP (75% of V
FB
)
FB
7
PG
-
+
22
TG1
Gate Driver
I
21
18
SWN1
V
CCP
AGND 4
6
COMP
8
V
DRP
9
10
0.8 V
19
Droop Amplifier
+
0.8 V
+
-
+
-
13
20
BG1
PGND1
CS1
CSN
CS2
BST2
14
11
-
+
+
-
15
Gate Driver
II
V
CCP
17
TG2
SWN2
R
OSC
1
OSCILLATOR
BG2
I
LIM
2
+
-
Fault
Logic
+
-
UVLO
16
24
PGND2
PG
EN
V
CC
12
3
+
9V
Figure 1. Simplified Block Diagram
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2
NCP5383
V
CC
NCP5383
R
OSC
I
LIM
PG
SS
V
CC
V
CCP
BST1
3
18
23
12 V
V
CCP
1
2
24
5
5V
TG1
SWN1
22
21
V
core
BG1
19
PGND1
20
V
CCP
V
CC
7
V
FB
BST2
13
14
15
V
core
TG2
SWN2
6
8
9
10
COMP
V
DRP
CS1
BG2
17
PGND2
CSN
EN
11
CS2
AGND
16
12
4
Figure 2. Typical Application Schematic
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3
NCP5383
PIN DESCRIPTIONS
Pin No.
1
Symbol
R
OSC
Description
A resistance from this pin to ground programs the oscillator frequency according to
f
SW
= 1 / (R
OSC
w
100 pF).
Also, this pin supplies a trimmed output voltage of 2.00 V so it may be used to form a voltage divider at the I
LIM
pin to set the over current shutdown threshold as shown in the Applications Schematics.
Over current shutdown threshold. To program the shutdown threshold, connect this pin to the R
OSC
pin via a
resistor divider as shown in the Applications Schematics. To disable the over current feature connect this pin
directly to the R
OSC
pin. To guarantee correct operation, this pin should only be connected to the voltage
generated by the R
OSC
pin – do not connect this pin to any externally generated voltages.
Power for the internal control circuits.
Power supply return for the analog circuits that control output voltage.
A capacitor from this pin to ground programs the soft-start time.
Output of the error amplifier and input to the inverting pin of the PWM comparators.
Voltage feedback pin and error amplifier inverting input. Connect a resistor from this pin to V
CORE
. The value of
this resistor and the amount of current from the droop resistor (R
DRP
) will set the amount of output voltage
droop (AVP) during load.
Current signal output for Adaptive Voltage Positioning (AVP). The offset of this pin above the no-load set-point
is proportional to the output current. Connect a resistor from this pin to V
FB
to set the amount of AVP current
into the feedback resistor (R
FB
) that will result in output voltage droop. Leave this pin open for no AVP.
Non-inverting input to current sense amplifier #x, x = 1, 2
Inverting input to current sense amplifier #x, x = 1 (Tie to V
CORE
)
When this pin is pulled High the controller is enabled. When it is pulled Low the controller will be disabled.
Either an open-collector output (with a pull-up resistor) or a logic gate (CMOS or totem-pole output) may be
used to drive this pin. A Low to High transition on this pin will induce soft start. If the Enable function is not
required, this pin should be tied directly to V
CCP
.
Power for the gate drivers
Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-channel MOSFET.:
Phase #x, x = 1, 2
Ground reference for the bottom gate drivers
Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top
MOSFET. : Phase #x, x = 1, 2
Top gate MOSFET driver pin. Connect this pin to the gate of the top N-channel MOSFET. : : Phase #x, x = 1,2
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the
PHASE pin. Typical values for CBST range from 0.1
mF
to 1
mF.
Ensure that CBST is placed near the IC.:
Phase #x, x = 1, 2.
PowerGood output. Open drain type output with internal delays. The output is latched low if V
fb
is 125% of V
FB
or 75% of V
FB
.
2
I
LIM
3
4
5
6
7
V
CC
AGND
SS
COMP
V
FB
8
V
DRP
9
10
12
CSx
CSxN
EN
18
19, 17
20, 16
21, 15
22, 14
23, 13
V
CCP
BG
PGND
SWN
TG
BST
24
PG
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4
NCP5383
ABSOLUTE MAXIMUM RATINGS
Rating
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature Soldering, Reflow (60 second maximum above 183°C):
Thermal Resistance, Junction-to-Ambient (R
qJA
) on a thermally conductive PCB in free air
ESD Susceptibility (Human Body Model)
JEDEC Moisture Sensitivity Level
Maximum Voltage V
CC
with respect to AGND
Maximum Voltage V
CCP
and all other pins with respect to ground
Maximum Voltage V
BST
and all other pins with respect to ground
Maximum Voltage V
BST
and all other pins with respect to SWN
Maximum Voltage SWN and all other pins with respect to ground
Minimum Voltage SWN and all other pins with respect to ground
Minimum Voltage all pins with respect to ground
Maximum Current into pins: COMP, V
DRP
Maximum Current out of pins: COMP, V
DRP
, R
OSC
, SS
Value
0 to 70
0 to 125
-55 to 150
230
56
2.0
1
13.2
5.5
18.7
5.5
3.0
-2.0
-0.3
3.0
3.0
Unit
°C
°C
°C
°C
°C/W
kV
MSL
V
V
V
V
V
V
V
mA
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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5
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