74VHCT373A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 6.4 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHCT373AMTR
74VHCT373ATTR
DESCRIPTION
The 74VHCT373A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
Figure 1: Pin Connection And IEC Logic Symbols
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
December 2004
Rev. 4
1/13
74VHCT373A
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage (see note 1)
DC Output Voltage (see note 2)
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) Output in OFF State
2) High or Low State
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage (see note 1)
Output Voltage (see note 2)
Operating Temperature
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
±
0.5V)
Parameter
Value
4.5 to 5.5
0 to 5.5
0 to 5.5
0 to V
CC
-55 to 125
0 to 20
Unit
V
V
V
V
°C
ns/V
1) Output in OFF State
2) High or Low State
3) V
IN
from 0.8V to 2V
3/13
74VHCT373A
Table 8: Capacitive Characteristics
Test Condition
Symbol
Parameter
T
A
= 25°C
Min.
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
Typ.
4
9
14
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
pF
Unit
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Latch)
Table 9: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
T
A
= 25°C
Min.
Typ.
0.6
-0.9
C
L
= 50 pF
2.0
-0.6
V
Max.
0.9
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
5.0
5.0
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
5/13
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