74VHC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74VHC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS technology.
A signal on the D INPUT is transferred to the Q
OUTPUTS during the positive going transition of
the clock pulse.
Figure 1: Pin Connection And IEC Logic Symbols
O
et
l
so
b
ro
P
e
uc
d
s)
t(
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
te
le
ro
P
uc
d
s)
t(
T&R
74VHC74MTR
74VHC74TTR
November 2004
Rev. 4
1/14
74VHC74
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
1, 13
2, 12
3, 11
SYMBOL
1CLR, 2CLR
1D, 2D
1CK, 2CK
NAME AND FUNCTION
Asynchronous Reset -
Direct Input
Data Inputs
Clock Input
(LOW to HIGH, Edge
Triggered)
Asynchronous Set - Direct
Input
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
Ground (0V)
Positive Supply Voltage
4, 10
5, 9
6, 8
7
14
1PR, 2PR
1Q, 2Q
1Q, 2Q
GND
V
CC
Table 3: Truth Table
INPUTS
CLR
L
H
L
H
H
H
X : Don’t Care
OUTPUTS
D
X
X
X
L
H
X
CK
X
X
X
Q
L
H
H
L
H
PR
H
L
L
H
H
H
Figure 3: Logic Diagram
O
et
l
so
b
ro
P
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uc
d
s)
t(
O
-
Q
n
so
b
te
le
Q
H
L
H
L
Q
n
H
ro
P
uc
d
s)
t(
FUNCTION
CLEAR
PRESET
NO CHANGE
This logic diagram has not be used to estimate propagation delays
2/14
74VHC74
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
Parameter
1) V
IN
from 30% to 70% of V
CC
O
et
l
so
b
ro
P
e
uc
d
s)
t(
O
-
s
b
te
le
o
Value
2 to 5.5
0 to 5.5
ro
P
uc
d
s)
t(
Unit
V
V
V
°C
ns/V
0 to V
CC
0 to 100
0 to 20
-55 to 125
3/14
74VHC74
Table 7: AC Electrical Characteristics
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
W
t
W
t
s
t
h
t
REM
f
MAX
CK Pulse Width
HIGH or LOW
PR or CLR Pulse
Width LOW
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
C
L
(pF)
15
50
15
50
15
50
15
50
T
A
= 25°C
Min.
Typ.
6.7
9.2
4.6
6.1
7.6
10.1
4.8
6.3
Max.
11.9
15.4
7.3
9.3
12.3
15.8
7.7
9.7
6.0
5.0
6.0
5.0
Value
-40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
14.0
17.5
8.5
10.5
14.5
18.0
9.0
11.0
7.0
-55 to 125°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
14.0
17.5
8.5
10.5
14.5
18.0
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
Setup Time D to CK 3.3
(*)
HIGH or LOW
5.0
(**)
Hold Time D to CK 3.3
(*)
HIGH or LOW
5.0
(**)
Removal Time
3.3
(*)
PR or CLR to CK
5.0
(**)
Maximum Clock
3.3
(*)
Frequency
3.3
(*)
15
50
15
50
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
Table 8: Capacitive Characteristics
Symbol
O
et
l
so
b
r
P
e
V
CC
(V)
5.0
5.0
5.0
(**)
5.0
(**)
od
uc
)-
(s
t
b
O
125
75
170
115
so
6.0
5.0
0.5
0.5
5.0
3.0
t
le
70
45
110
75
P
e
5.0
7.0
5.0
7.0
5.0
0.5
0.5
5.0
3.0
ro
uc
d
9.0
11.0
7.0
5.0
7.0
5.0
7.0
5.0
0.5
0.5
5.0
3.0
s)
t(
ns
ns
ns
ns
ns
ns
80
50
70
45
110
75
MHz
130
90
Test Condition
T
A
= 25°C
Min.
Typ.
7
f
IN
= 10MHz
25
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
Parameter
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
flip-flop)
5/14
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