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74VHC238

产品描述3 TO 8 LINE DECODER
文件大小212KB,共12页
制造商ST(意法半导体)
官网地址http://www.st.com/
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74VHC238概述

3 TO 8 LINE DECODER

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74VHC238
3 TO 8 LINE DECODER
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 238
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74VHC238 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go high. If enable input G1 is held low or either
G2A or G2B is held high, decoding function is
inhibited and all the 8 outputs go to low.
Figure 1: Pin Connection And IEC Logic Symbols
O
et
l
so
b
ro
P
e
uc
d
s)
t(
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
te
le
ro
P
uc
d
s)
t(
T&R
74VHC238MTR
74VHC238TTR
November 2004
Rev. 4
1/12

74VHC238相似产品对比

74VHC238 74VHC238_04
描述 3 TO 8 LINE DECODER 3 TO 8 LINE DECODER

 
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