74VHC16373
16-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS NON INVERTING
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
TSSOP
ORDER CODES
PACKAGE
TSSOP
PIN CONNECTION
bs
O
DESCRIPTION
The 74VHC16373 is an advanced high-speed
CMOS 16 BIT D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
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T&R
74VHC16373TTR
February 2003
1/11
74VHC16373
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
SYMBOL
1OE
NAME AND FUNCTION
IEC LOGIC SYMBOLS
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs
11, 12
13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs
19, 20, 22, 23
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48
1LE
Latch Enable Input
4, 10, 15, 21,
GND
Ground (0V)
28, 34, 39, 45
7, 18, 31, 42
V
CC
Positive Supply Voltage
bs
O
H
L
L
L
TRUTH TABLE
INPUTS
LE
X
L
H
H
D
X
X
L
H
OUTPUT
Q
Z
NO CHANGE *
L
H
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OE
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
2/11
74VHC16373
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
bs
O
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Parameter
Value
2 to 5.5
0 to 5.5
0 to V
CC
-55 to 125
0 to 100
0 to 20
Unit
V
V
V
°C
ns/V
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t(
Unit
V
V
V
mA
mA
mA
mA
°C
°C
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
75
-65 to +150
300
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
1) V
IN
from 30% to 70% of V
CC
3/11
74VHC16373
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PLH
t
PHL
Propagation Delay
Time
Dn to Qn
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PLZ
t
PHZ
t
w
t
s
t
h
t
OSLH
t
OSHL
Output Disable
Time
Pulse Width (LE)
HIGH
Setup Time Dn to
LE HIGH or LOW
Hold Time Dn to LE
HIGH or LOW
Output to Output
Skew time (note 1)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
T
A
= 25°C
Min.
Typ.
5.5
7
3.6
5
5.5
7.5
4
5
5.2
7.6
4
5
9
6
Max.
13
14.5
8.5
9.5
13
14
8.2
9.2
13
14.9
9.1
10.1
15.5
10.5
Value
-40 to 85°C
Min.
1
1
1
1
1
1
1
1
1
Max.
15
16.5
9.5
10.5
15
16
9.5
10.5
15
-55 to 125°C
Min.
1
1
1
1
1
1
1
1
1
Max.
15
16.5
9.5
10.5
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
LE to Qn
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
bs
O
C
IN
CAPACITIVE CHARACTERISTICS
Test Condition
Parameter
V
CC
(V)
T
A
= 25°C
Min.
Typ.
2.5
4
5.0
f
IN
= 10MHz
21
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
pF
Unit
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(s
t
b
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5
5
4
4
1
1
so
te
le
r
P
1
1
1
1
1
5
5
4
4
1
1
d
o
16
10
11.5
17
11.5
uc
1
1
1
1
1
5
5
4
4
1
1
s)
t(
16
9.5
10.5
15
16
10
11.5
17
11.5
15
ns
ns
ns
ns
ns
ns
ns
1.5
1
50
50
1.5
1
1.5
1
ns
Symbol
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
C
OUT
C
PD
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per Latch)
5/11
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