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74V1G126_04

产品描述LOGIC GATE|BUFFER|CMOS|TSOP|6PIN|PLASTIC
文件大小125KB,共10页
制造商ST(意法半导体)
官网地址http://www.st.com/
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74V1G126_04概述

LOGIC GATE|BUFFER|CMOS|TSOP|6PIN|PLASTIC

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74V1G126
SINGLE BUS BUFFER (3-STATE)
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.4ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74V1G126STR
74V1G126CTR
DESCRIPTION
The 74V1G126 is an advanced high-speed CMOS
SINGLE BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
3-STATE control input 1G has to be set LOW to
place the output into the high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2004
1/10

74V1G126_04相似产品对比

74V1G126_04 74V1G126
描述 LOGIC GATE|BUFFER|CMOS|TSOP|6PIN|PLASTIC LOGIC GATE|BUFFER|CMOS|TSOP|6PIN|PLASTIC

 
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