64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
SST38VF640x2.7V 64Mb (x16) MPF+ memories
Preliminary Specification
FEATURES:
• Organized as 4M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: up to 100,000 Cycles minimum
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 4 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• 128-bit Unique ID
• Security-ID Feature
– 256 Word, user One-Time-Programmable
• Protection and Security Features
– Hardware Boot Block Protection/WP# Input Pin,
Uniform (32 KWord) and Non-Uniform (8 KWord)
options available
– User-controlled individual block (32 KWord) pro-
tection, using software only methods
– Password protection
• Hardware Reset Pin (RST#)
• Fast Read and Page Read Access Times:
– 90 ns Read access time
– 25 ns Page Read access times
- 4-Word Page Read buffer
• Latched Address and Data
• Fast Erase Times:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
• Erase-Suspend/-Resume Capabilities
• Fast Word and Write-Buffer Programming
Times:
– Word-Program Time: 7 µs (typical)
– Write Buffer Programming Time: 1.75 µs / Word
(typical)
- 16-Word Write Buffer
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– RY/BY# Output
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• CFI Compliant
• Packages Available
– 48-lead TSOP
– 48-ball TFBGA
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST38VF6401, SST38VF6402, SST38VF6403, and
SST38VF6404 devices are 4M x16 CMOS Advanced
Multi-Purpose Flash Plus (Advanced MPF+) manufactured
with SST proprietary, high-performance CMOS Super-
Flash technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufacturabil-
ity compared with alternate approaches. The
SST38VF6401/6402/6403/6404 write (Program or Erase)
with a 2.7-3.6V power supply. These devices conform to
JEDEC standard pin assignments for x16 memories.
Featuring high performance Word-Program, the
SST38VF6401/6402/6403/6404 provide a typical Word-
Program time of 7 µsec. For faster word-programming per-
formance, the Write-Buffer Programming feature, has a typ-
ical word-program time of 1.75 µsec. These devices use
Toggle Bit or Data# Polling to indicate Program operation
completion. In addition to single-word Read, Advanced
MPF+ devices provide a Page-Read feature that enables a
faster word read time of 25 ns, for words on the same page.
To protect against inadvertent write, the SST38VF6401/
6402/6403/6404 have on-chip hardware and Software
Data Protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, these devices
are available with up to 100,000 cycles minimum endur-
ance. Data retention is rated at greater than 100 years.
The SST38VF6401/6402/6403/6404 are suited for applica-
tions that require the convenient and economical updating
of program, configuration, or data memory. For all system
applications, Advanced MPF+ significantly improve perfor-
mance and reliability, while lowering power consumption.
These devices inherently use less energy during Erase and
Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. For any given voltage range,
the SuperFlash technology uses less current to program
and has a shorter erase time; therefore, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies.
©2008 Silicon Storage Technology, Inc.
S71309-03-000
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1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Preliminary Specification
These devices also improve flexibility while lowering the
cost for program, data, and configuration storage applica-
tions. The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/Pro-
gram cycles that have occurred. Therefore, the system soft-
ware or hardware does not have to be modified or de-rated
as is necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST38VF6401/6402/6403/6404 also offer flexible data
protection features. Applications that require memory pro-
tection from program and erase operations can use the
Boot Block, Individual Block Protection, and Advanced Pro-
tection features. For applications that require a permanent
solution, the Irreversible Block Locking feature provides
permanent protection for memory blocks.
To meet high-density, surface mount requirements, the
SST38VF6401/6402/6403/6404 devices are offered in 48-
lead TSOP and 48-ball TFBGA packages. See Figures 2
and 3 for pin assignments and Table 7 for pin descriptions.
when either CE# or OE# is high. Refer to Figure 5, the
Read cycle timing diagram, for further details.
Page Read
The Page Read operation utilizes an asynchronous
method that enables the system to read data from the
SST38VF6401/6402/6403/6404 at a faster rate. This oper-
ation allows users to read a four-word page of data at an
average speed of 41.25 ns per word.
In Page Read, the initial word read from the page requires
T
ACC
to be valid, while the remaining three words in the
page require only T
PACC
. All four words in the page have
the same address bits, A
21
-A
2
, which are used to select the
page. Address bits A
1
and A
0
are toggled, in any order, to
read the words within the page.
The Page Read operation of the SST38VF6401/6402/
6403/6404 is controlled by CE# and OE#. Both CE# and
OE# must be low for the system to obtain data from the
output pins. CE# controls device selection. When CE# is
high, the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to Figure 6,
the Page Read cycle timing diagram, for further details.
DEVICE OPERATION
The memory operations functions of these devices are initi-
ated using commands written to the device using standard
microprocessor Write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
The SST38VF6401/6402/6403/6404 also have the Auto
Low Power mode which puts the device in a near-standby
mode after data has been accessed with a valid Read
operation. This reduces the I
DD
active read current from
typically 4 mA to typically 3 µA. The Auto Low Power mode
reduces the typical I
DD
active read current to the range of 2
mA/MHz of Read cycle time. The device requires no
access time to exit the Auto Low Power mode after any
address transition or control signal transition used to initiate
another Read cycle. The device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Word-Program Operation
The SST38VF6401/6402/6403/6404 can be programmed
on a word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program
operation is accomplished in three steps. The first step is the
three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During
the Word-Program operation, the addresses are latched on
the falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Program
operation which is initiated after the rising edge of the fourth
WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figures 7
and 8 for WE# and CE# controlled Program operation timing
diagrams and Figure 24 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling, Toggle Bits, and RY/BY#. During the internal
Program operation, the host is free to perform additional
tasks. Any commands issued during the internal Program
operation are ignored. During the command sequence,
WP# should be statically held high or low.
When programming more than a few words, SST recom-
mends Write-Buffer Programming.
Read
The Read operation of the SST38VF6401/6402/6403/
6404 is controlled by CE# and OE#, both of which have
to be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
©2008 Silicon Storage Technology, Inc.
S71309-03-000
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64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Preliminary Specification
Write-Buffer Programming
The SST38VF6401/6402/6403/6404 offer Write-Buffer
Programming, a feature that enables faster effective word
programming. To use this feature, write up to 16 words with
the Write-to-Buffer command, then use the Program
Buffer-to-Flash command to program the Write-Buffer to
memory.
The Write-to-Buffer command consists of between 5 and
20 write cycles. The total number of write cycles in the
Write-to-Buffer command sequence is equal to the number
of words to be written to the buffer plus four.
The first three cycles in the command sequence tell the
device that a Write-to-Buffer operation will begin.
The fourth cycle tells the device the number of words to be
written into the buffer and the block address of these words.
Specifically, the write cycle consists of a block address and
a data value called the Word Count (WC), which is the
number of words to be written to the buffer minus one. If the
WC is greater than 15, the maximum buffer size minus 1,
then the operation aborts.
For the fifth cycle, and all subsequent cycles of the Write-
to-Buffer command, the command sequence consists of
the addresses and data of the words to be written into the
buffer. All of these cycles must have the same A
21
- A
4
address, otherwise the operation aborts. The number of
Write cycles required is equal to the number of words to be
written into the Write-Buffer, which is equal to WC plus one.
The correct number of Write cycles must be issued or the
operation will abort. Each Write cycle decrements the
Write-Buffer counter, even if two or more of the Write cycles
have identical address values. Only the final data loaded for
each buffer location is held in the Write-Buffer.
Once the Write-to-Buffer command sequence is com-
pleted, the Program Buffer-to-Flash command should be
issued to program the Write-Buffer contents to the speci-
fied block in memory. The block address (i.e. A
21
- A
15
) in
this command must match the block address in the 4th
write cycle of the Write-to-Buffer command or the operation
aborts. See Table 11 for details on Write-to-Buffer and Pro-
gram-Buffer-to-Flash commands.
While issuing these command sequences, the Write-Buffer
Programming Abort detection bit (DQ1) indicates if the
operation has aborted. There are several cases in which
the device can abort:
•
In the fourth write cycle of the Write-to-Buffer com-
mand, if the WC is greater than 15, the operation
aborts.
•
In the fifth and all subsequent cycles of the Write-to-
Buffer command, if the address values, A
21
- A
4
, are
not identical, the operation aborts.
•
If the number of write cycles between the fifth to the
last cycle of the Write-to-Buffer command is greater
than WC +1, the operation aborts.
After completing the Write-to-Buffer command
sequence, issuing any command other than the Pro-
gram Buffer-to-Flash command, aborts the operation.
Loading a block address, i.e. A
21
-A
15,
in the Program
Buffer-to-Flash command that does not match the
block address used in the Write-to-Buffer command
aborts the operation.
•
•
If the Write-to-Buffer or Program Buffer-to-Flash operation
aborts, then DQ
1
= 1 and the device enters Write-Buffer-
Abort mode. To execute another operation, a Write-to-
Buffer Abort-Reset command must be issued to clear DQ
1
and return the device to standard read mode.
After the Write-to-Buffer and Program Buffer-to-Flash
commands are successfully issued, the programming
operation can be monitored using Data# Polling, Toggle
Bits, and RY/BY#.
Sector/Block-Erase Operations
The Sector-Erase and Block-Erase operations allow the
system to erase the device on a sector-by-sector, or block-
by-block, basis. The SST38VF6401/6402/6403/6404 offer
both Sector-Erase and Block-Erase modes.
The Sector-Erase architecture is based on a sector size of
4 KWords. The Sector-Erase command can erase any 4
KWord sector (S0 - S1023).
The Block-Erase architecture is based on block size of 32
KWords. In SST38VF6401 and SST38VF6402 devices,
the Block-Erase command can erase any 32KWord Block
(B0-B127). For the non-uniform boot block devices,
SST38VF6403 and SST38VF6404, the Block-Erase com-
mand can erase any 32 KWord block except the block that
contains the boot area. In the boot area, Block-Erase
behaves like Sector-Erase, and only erases a 4KWord sec-
tor. For the SST38VF6403 device, a Block-Erase executed
on the Boot Block (B0), will result in the device erasing a
4KWord sector in B0 located at A
21
-A
12
. For the
SST38VF6404 device, a Block-Erase executed on the
Boot Block (B127), will result in the device erasing a
4KWord sector in B127 located at A
21
-A
12
.
The Sector-Erase operation is initiated by executing a six-
byte command sequence with Sector-Erase command
(50H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (30H)
and block address (BA) in the last bus cycle. The sector or
block address is latched on the falling edge of the sixth
S71309-03-000
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©2008 Silicon Storage Technology, Inc.
3
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Preliminary Specification
WE# pulse, while the command (50H or 30H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. The RY/BY# pin can also be
used to monitor the erase operation. For more information,
see Figures 14 and 15 for timing waveforms and Figure 29
for the flowchart.
Any commands, other than Erase-Suspend, issued during
the Sector- or Block-Erase operation are ignored.
Any
attempt to Sector- or Block-Erase memory inside a block
protected by Volatile Block Protection, Non-Volatile Block
Protection, or WP# (low) will be ignored. During the com-
mand sequence, WP# should be statically held high or low.
resume an Erase operation, the Bypass mode must be
exited before issuing Erase-Resume. For more information
about Bypass mode, see “Bypass Mode” on page 7.
Chip-Erase Operation
The SST38VF6401/6402/6403/6404 devices provide a
Chip-Erase operation, which erases the entire memory
array to the ‘1’ state. This operation is useful when the
entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid reads are Toggle Bit, Data# Poll-
ing, or RY/BY#. See Table 11 for the command sequence,
Figure 13 for timing diagram, and Figure 29 for the flow-
chart. Any commands issued during the Chip-Erase oper-
ation are ignored. If WP# is low, or any VPBs or NVPBs
are in the protect state, any attempt to execute a Chip-
Erase operation is ignored. During the command
sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sec-
tor- or Block-Erase operation thus allowing data to be read
or programmed into any sector or block that is not engaged
in an Erase operation. The operation is executed with a one-
byte command sequence with Erase-Suspend command
(B0H). The device automatically enters read mode within 20
µs (max) after the Erase-Suspend command had been
issued. Valid data can be read, using a Read or Page Read
operation, from any sector or block that is not being erased.
Reading at an address location within Erase-Suspended
sectors or blocks will output DQ
2
toggling and DQ
6
at ‘1’.
While in Erase-Suspend, a Word-Program or Write-Buffer
Programming operation is allowed anywhere except the
sector or block selected for Erase-Suspend.
To resume a suspended Sector-Erase or Block-Erase oper-
ation, the system must issue the Erase-Resume command.
The operation is executed by issuing one byte command
sequence with Erase-Resume command (30H) at any
address in the last Byte sequence.
When an erase operation is suspended, or re-suspended,
after resume the cumulative time needed for the erase
operation to complete is greater than the erase time of a
non-suspended erase operation. If the hold time from
Erase-Resume to the next Erase- Suspend operation is
less than 200µs, the accumulative erase time can become
very long Therefore, after issuing an Erase-Resume com-
mand, the system must wait at least 200µs before issuing
another Erase-Suspend command. The Erase-Resume
command will be ignored until any program operations initi-
ated during Erase-Suspend are complete.
Bypass mode can be entered while in Erase-Suspend, but
only Bypass Word-Program is available for those sectors or
blocks that are not suspended. Bypass Sector-Erase,
Bypass Block-Erase, and Bypass Chip-Erase, Erase-Sus-
pend, and Erase-Resume are not available. In order to
©2008 Silicon Storage Technology, Inc.
Write Operation Status Detection
To optimize the system Write cycle time, the
SST38VF6401/6402/6403/6404 provide two software
means to detect the completion of a Write (Program or
Erase) cycle The software detection includes two status
bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-
Write detection mode is enabled after the rising edge of
WE#, which initiates the internal Program or Erase opera-
tion.
The actual completion of the nonvolatile write is asyn-
chronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the completion
of the write cycle. If this occurs, the system may possibly
get an incorrect result from the status detection process.
For example, valid data may appear to conflict with either
DQ
7
or DQ
6
. To prevent false results, upon detection of
failures, the software routine should loop to read the
accessed location an additional two times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the failure is valid.
For the Write-Buffer Programming feature, DQ
1
informs
the user if either the Write-to-Buffer or Program Buffer-to-
Flash operation aborts. If either operation aborts, then
DQ
1
= 1. DQ
1
must be cleared to '0' by issuing the Write-
to-Buffer Abort Reset command.
S71309-03-000
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64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Preliminary Specification
The SST38VF6401/6402/6403/6404 also provide a RY/
BY# signal. This signal indicates the status of a Program or
Erase operation.
If a Program or Erase operation is attempted on a pro-
tected sector or block, the operation will abort. After the
device initiates an abort, the corresponding Write Opera-
tion Status Detection Bits will stay active for approximately
200ns (program or erase) before the device returns to read
mode.
For the status of these bits during a Write operation, see
Table 1.
Data# Polling (DQ
7
)
When the SST38VF6401/6402/6403/6404 are in an inter-
nal Program operation, any attempt to read DQ
7
will pro-
duce the complement of true data. For a Program Buffer-
to-Flash operation, DQ7 is the complement of the last
word loaded in the Write-Buffer using the Write-to-Buffer
command. Once the Program operation is completed,
DQ
7
will produce valid data. Note that even though DQ
7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid. Valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs.
During an internal Erase operation, any attempt to read
DQ
7
will produce a ‘0’. Once the internal Erase operation
is completed, DQ
7
will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 11 for Data# Polling timing dia-
gram and Figure 26 for a flowchart.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit
(DQ
6
) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ
6
will be set to ‘1’ if a Read operation is attempted
on an Erase-Suspended Sector or Block. If Program oper-
ation is initiated in a sector/block not selected in Erase-Sus-
pend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector or block is being actively erased or erase-sus-
pended. Table 1 shows detailed bit status information. The
Toggle Bit (DQ
2
) is valid after the rising edge of the last
WE# (or CE#) pulse of Write operation. See Figure 12 for
Toggle Bit timing diagram and Figure 26 for a flowchart.
DQ
1
If an operation aborts during a Write-to-Buffer or Program
Buffer-to-Flash operation, DQ
1
is set to ‘1’. To reset DQ
1
to
‘0’, issue the Write-to-Buffer Abort Reset command to exit
the abort state. A power-off/power-on cycle or a Hardware
Reset (RST# = 0) will also clear DQ
1
.
RY/BY#
The RY/BY# pin can be used to determine the status of a
Program or Erase operation. The RY/BY# pin is valid after
the rising edge of the final WE# pulse in the command
sequence. If RY/BY# = 0, then the device is actively pro-
gramming or erasing. If RY/BY# = 1, the device is in Read
mode. The RY/BY# pin is an open drain output pin. This
means several RY/BY# can be tied together with a pull-up
resistor to V
DD..
DQ
6
Toggle
Toggle
No toggle
Data
Toggle
Toggle
Toggle
DQ
2
1
No Toggle
Toggle
Toggle
Data
N/A
N/A
N/A
0
N/A
N/A
Data
N/A
0
1
DQ
1
0
0
1
1
0
0
0
T1.0 1309
TABLE 1: Write Operation Status
Status
Normal
Operation
Erase-Suspend
Mode
Standard Program
Standard Erase
Read from Erase-Suspended
Sector/Block
Read from Non- Erase-
Suspended Sector/Block
Program
Program Buffer-
to-Flash
Busy
Abort
0
1
Data
DQ
7
#
DQ
7
#
3
DQ
7
#
3
DQ
71
DQ
7
#
RY/BY#
2
1. DQ
7
and DQ
2
require a valid address when reading status information.
2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode.
3. During a Program Buffer-to-Flash operation, the datum on the DQ
7
pin is the complement of DQ
7
of the last word loaded in the Write-
Buffer using the Write-to-Buffer command.
©2008 Silicon Storage Technology, Inc.
S71309-03-000
08/08
5
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