74LVX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH PRESET AND CLEAR (5V TOLERANT INPUTS)
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED :
f
MAX
= 145MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL :
V
IL
=0.8V, V
IH
=2V AT V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX74M
T&R
74LVX74MTR
74LVX74TTR
DESCRIPTION
The 74LVX74 is a low voltage CMOS DUAL
D-TYPE FLIP-FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse. CLR and PR are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
July 2001
1/11
74LVX74
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 2) (V
CC
= 3.3V)
Parameter
Value
2 to 3.6
0 to 5.5
0 to V
CC
-55 to 125
0 to 100
Unit
V
V
V
°C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
V
OL
Low Level Output
Voltage
2.0
3.0
3.0
I
I
I
CC
Input Leakage
Current
Quiescent Supply
Current
3.6
3.6
I
O
=-50
µA
I
O
=-50
µA
I
O
=-4 mA
I
O
=50
µA
I
O
=50
µA
I
O
=4 mA
V
I
= 5V or GND
V
I
= V
CC
or GND
T
A
= 25°C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
±
0.1
2
2.0
3.0
1.9
2.9
2.48
0.1
0.1
0.44
±
1
20
Typ.
Max.
Value
-40 to 85°C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.4
0.1
0.1
0.55
±
1
20
µA
µA
V
V
Max.
-55 to 125°C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
V
Max.
V
Unit
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IL
V
OH
3/11
74LVX74
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
2.7
3.3
(*)
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
3.3
(*)
2.7
3.3
(*)
C
L
(pF)
15
50
15
50
15
50
15
50
50
50
50
50
50
50
50
50
50
50
15
50
15
50
50
50
55
45
95
60
135
60
145
85
0.5
0.5
1.0
1.0
T
A
= 25°C
Min.
Typ.
7.3
9.8
5.7
8.2
8.4
10.9
6.6
9.1
Max.
15.0
18.5
9.7
13.2
15.6
19.1
10.1
13.6
8.5
6.0
8.5
6.0
8.0
5.5
0.5
0.5
6.5
5.0
50
40
80
50
1.5
1.5
Value
-40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
18.5
22.0
11.5
15.0
18.5
22.0
12.0
15.5
10.0
7.0
10.0
7.0
9.5
6.5
0.5
0.5
7.5
5.0
50
40
80
50
1.5
1.5
ns
MHz
-55 to 125°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
18.5
22.0
11.5
15.0
18.5
22.0
12.0
15.5
10.0
7.0
10.0
7.0
9.5
6.5
0.5
0.5
7.5
5.0
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time CK to
Q or Q
t
PLH
t
PHL
Propagation Delay
Time
PR or CLR to
Q or Q
t
w
Minimum Pulse
Width HIGH or
LOW, CK
Minimum Pulse
Width LOW
PR or CLR
Minimum Setup
Time D to CK
HIGH or LOW
Minimum Hold
Time D to CK
HIGH or LOW
Minimum Removal
Time PR or CLR to
CK
Maximum Clock
Frequency
t
w(L)
ns
t
s
ns
t
h
ns
t
REM
ns
f
MAX
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
f
IN
= 10 MHz
T
A
= 25°C
Min.
Typ.
4
25
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per circuit)
5/11
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